Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11973630 | Calibrating a quadrature receive serial interface | Daniel M. Dreps, Erik English, Jieming Qi, Michael A. Sperling | 2024-04-30 |
| 11907074 | Low-latency deserializer having fine granularity and defective-lane compensation | Patrick J. Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan I. Friedman +2 more | 2024-02-20 |
| 11099601 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Susan M. Eickhoff, Gary A. Van Huben, Stephen D. Wyatt | 2021-08-24 |
| 10901936 | Staged power on/off sequence at the I/O phy level in an interchip interface | Daniel M. Dreps, Prasanna Jayaraman | 2021-01-26 |
| 10771068 | Reducing chip latency at a clock boundary by reference clock phase adjustment | Steven R. Carlough, Susan M. Eickhoff, Michael W. Harper, Gary A. Van Huben | 2020-09-08 |
| 10698440 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Susan M. Eickhoff, Gary A. Van Huben, Stephen D. Wyatt | 2020-06-30 |
| 10608763 | Built-in self-test for receiver channel | John G. Rell, III, Michael W. Harper, Mack W. Riley | 2020-03-31 |
| 10162773 | Double data rate (DDR) memory read latency reduction | Steven R. Carlough, Susan M. Eickhoff, Gary A. Van Huben, Stephen D. Wyatt | 2018-12-25 |
| 9715270 | Power reduction in a parallel data communications interface using clock resynchronization | Steven J. Baumgartner, Daniel M. Dreps | 2017-07-25 |
| 9474034 | Power reduction in a parallel data communications interface using clock resynchronization | Steven J. Baumgartner, Daniel M. Dreps | 2016-10-18 |
| 9092312 | System and method to inject a bit error on a bus lane | Patrick J. Meaney, Kenneth L. Wright | 2015-07-28 |
| 8898504 | Parallel data communications mechanism having reduced power continuously calibrated lines | Steven J. Baumgartner, Frank D. Ferraiolo, Susan M. Eickhoff | 2014-11-25 |
| 8767531 | Dynamic fault detection and repair in a data communications mechanism | Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow | 2014-07-01 |
| 8681839 | Calibration of multiple parallel data communications lines for high skew conditions | John F. Bulzacchelli, Timothy O. Dickson, Frank D. Ferraiolo, Robert J. Reese | 2014-03-25 |
| 8139430 | Power-on initialization and test for a cascade interconnect memory system | Peter Buchmann, Frank D. Ferraiolo, Kevin C. Gower, Robert J. Reese, Eric E. Retter +3 more | 2012-03-20 |
| 8001412 | Combined alignment scrambler function for elastic interface | Frank D. Ferraiolo, Robert J. Reese | 2011-08-16 |
| 7412618 | Combined alignment scrambler function for elastic interface | Frank D. Ferraiolo, Robert J. Reese | 2008-08-12 |