Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12088314 | Segmented digital-to-analog converter wireline driver | Martin Cochet, Marcel A. Kossel, John F. Bulzacchelli, Zeynep Toprak-Deniz | 2024-09-10 |
| 12015510 | Transmitter with uniform driver segment activity | Martin Cochet, Zeynep Toprak-Deniz, John F. Bulzacchelli, Jonathan E. Proesel | 2024-06-18 |
| 11804828 | Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output | Jieming Qi, Daniel M. Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie E. Cox | 2023-10-31 |
| 10284363 | Serial transmitter with feed forward equalizer | Mounir Meghelli | 2019-05-07 |
| 10171281 | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases | Bongjin Kim | 2019-01-01 |
| 10097383 | High speed DFEs with direct feedback | John F. Bulzacchelli, Mounir Meghelli, Jonathan E. Proesel, Guanghua Shu | 2018-10-09 |
| 9942028 | Serial transmitter with feed forward equalizer and timing calibration | Mounir Meghelli | 2018-04-10 |
| 9942030 | Serial transmitter with feed forward equalizer | Mounir Meghelli | 2018-04-10 |
| 9876667 | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases | Bongjin Kim | 2018-01-23 |
| 9699009 | Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivity | Herschel A. Ainspan | 2017-07-04 |
| 9684629 | Efficient calibration of a low power parallel data communications channel | Daniel M. Dreps, Frank D. Ferraiolo, Douglas J. Joseph | 2017-06-20 |
| 9674025 | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases | Bongjin Kim | 2017-06-06 |
| 9411750 | Efficient calibration of a low power parallel data communications channel | Daniel M. Dreps, Frank D. Ferraiolo, Douglas J. Joseph | 2016-08-09 |
| 9325542 | Power-scalable skew compensation in source-synchronous parallel interfaces | Ankur Agrawal, Sergey V. Rylov | 2016-04-26 |
| 9001842 | Parallel receiver interface with receiver redundancy | Douglas J. Joseph, Frank D. Ferraiolo | 2015-04-07 |
| 8861513 | Fault tolerant parallel receiver interface with receiver redundancy | Daniel M. Dreps, Frank D. Ferraiolo | 2014-10-14 |
| 8842722 | Decision feedback equalizers with high-order continuous time feedback | Rui Yan Matthew Loh | 2014-09-23 |
| 8824540 | Decision feedback equalizers with high-order continuous time feedback | Rui Yan Matthew Loh | 2014-09-02 |
| 8774228 | Timing recovery method and apparatus for an input/output bus with link redundancy | John F. Bulzacchelli, Daniel J. Friedman, Yong Liu, Sergey V. Rylov | 2014-07-08 |
| 8681839 | Calibration of multiple parallel data communications lines for high skew conditions | John F. Bulzacchelli, Frank D. Ferraiolo, Robert J. Reese, Michael B. Spear | 2014-03-25 |
| 8085841 | Sampled current-integrating decision feedback equalizer and method | John F. Bulzacchelli, Daniel J. Friedman, Alexander V. Rylyakov | 2011-12-27 |