Issued Patents All Time
Showing 25 most recent of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176960 | Communication systems for power supply noise reduction | David J. Krolak, Daniel M. Dreps, Erik English, Michael A. Sperling | 2024-12-24 |
| 12095891 | Communication systems for power supply noise reduction | David J. Krolak, Daniel M. Dreps, Erik English, Michael A. Sperling | 2024-09-17 |
| 11979480 | Quadrature circuit interconnect architecture with clock forwarding | Michael A. Sperling, Daniel M. Dreps, Erik English | 2024-05-07 |
| 11973630 | Calibrating a quadrature receive serial interface | Michael B. Spear, Daniel M. Dreps, Erik English, Michael A. Sperling | 2024-04-30 |
| 11804828 | Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output | Daniel M. Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie E. Cox, Timothy O. Dickson | 2023-10-31 |
| 10608648 | Single-lock delay locked loop with cycle counter and method therefor | Aaron Willey | 2020-03-31 |
| 10250265 | Single-lock delay locked loop with cycle counter and method therefor | Aaron Willey | 2019-04-02 |
| 10056909 | Single-lock delay locked loop with cycle counter and method therefore | Aaron Willey | 2018-08-21 |
| 9444657 | Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations | Minhan Chen | 2016-09-13 |
| 8736304 | Self-biased high speed level shifter circuit | David William Boerstler, Eskinder Hailu, Kazuhiko Miki | 2014-05-27 |
| 8611368 | Controlling bandwidth reservations method and apparatus | Shigehiro Asano, Charles Ray Johns, Matthew KING, Peichun Peter Liu, David Mui | 2013-12-17 |
| 8483227 | Controlling bandwidth reservations method and apparatus | Shigehiro Asano, Charles Ray Johns, Matthew KING, Peichun Peter Liu, David Mui | 2013-07-09 |
| 8381143 | Structure for a duty cycle correction circuit | David William Boerstler, Eskinder Hailu | 2013-02-19 |
| 8201112 | Structure for managing voltage swings across field effect transistors | David William Boerstler | 2012-06-12 |
| 8183920 | Variable gain amplifier with reduced power consumption | David William Boerstler, Minhan Chen, Hayden C. Cranford, Jr. | 2012-05-22 |
| 8108813 | Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler | David William Boerstler, Eskinder Hailu, Masaaki Kaneko | 2012-01-31 |
| 8054119 | System and method for on/off-chip characterization of pulse-width limiter outputs | David William Boerstler, Eskinder Hailu | 2011-11-08 |
| 8041537 | Clock duty cycle measurement with charge pump without using reference clock calibration | Eskinder Hailu, David William Boerstler, Masaaki Kaneko | 2011-10-18 |
| 8037431 | Structure for interleaved voltage controlled oscillator | David William Boerstler, Eskinder Hailu, Mike Shen | 2011-10-11 |
| 8032850 | Structure for an absolute duty cycle measurement circuit | David William Boerstler, Eskinder Hailu, Masaaki Kaneko, Bin Wan | 2011-10-04 |
| 7994830 | Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction | Masaaki Kaneko, David William Boerstler, Eskinder Hailu | 2011-08-09 |
| 7969250 | Structure for a programmable interpolative voltage controlled oscillator with adjustable range | David William Boerstler, Eskinder Hailu, Masaaki Kaneko | 2011-06-28 |
| 7958469 | Design structure for a phase locked loop with stabilized dynamic response | David William Boerstler, Eskinder Hailu | 2011-06-07 |
| 7917795 | Digital circuit to measure and/or correct duty cycles | David William Boerstler, Eskinder Hailu, Byron L. Krauter, Kazuhiko Miki | 2011-03-29 |
| 7917318 | Structure for a duty cycle measurement circuit | David William Boerstler, Eskinder Hailu, Masaaki Kaneko, Bin Wan | 2011-03-29 |