| 12176960 |
Communication systems for power supply noise reduction |
David J. Krolak, Daniel M. Dreps, Erik English, Michael A. Sperling |
2024-12-24 |
$24,905,000 |
| 12095891 |
Communication systems for power supply noise reduction |
David J. Krolak, Daniel M. Dreps, Erik English, Michael A. Sperling |
2024-09-17 |
$9,971,000 |
| 11979480 |
Quadrature circuit interconnect architecture with clock forwarding |
Michael A. Sperling, Daniel M. Dreps, Erik English |
2024-05-07 |
$15,644,000 |
| 11973630 |
Calibrating a quadrature receive serial interface |
Michael B. Spear, Daniel M. Dreps, Erik English, Michael A. Sperling |
2024-04-30 |
$14,003,000 |
| 11804828 |
Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output |
Daniel M. Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie E. Cox, Timothy O. Dickson |
2023-10-31 |
$8,788,000 |
| 10608648 |
Single-lock delay locked loop with cycle counter and method therefor |
Aaron Willey |
2020-03-31 |
$278,000 |
| 10250265 |
Single-lock delay locked loop with cycle counter and method therefor |
Aaron Willey |
2019-04-02 |
$963,000 |
| 10056909 |
Single-lock delay locked loop with cycle counter and method therefore |
Aaron Willey |
2018-08-21 |
$1,340,000 |
| 9444657 |
Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations |
Minhan Chen |
2016-09-13 |
$4,023,000 |
| 8736304 |
Self-biased high speed level shifter circuit |
David William Boerstler, Eskinder Hailu, Kazuhiko Miki |
2014-05-27 |
$4,024,000 |
| 8611368 |
Controlling bandwidth reservations method and apparatus |
Shigehiro Asano, Charles Ray Johns, Matthew KING, Peichun Peter Liu, David Mui |
2013-12-17 |
$6,242,000 |
| 8483227 |
Controlling bandwidth reservations method and apparatus |
Shigehiro Asano, Charles Ray Johns, Matthew KING, Peichun Peter Liu, David Mui |
2013-07-09 |
$6,470,000 |
| 8381143 |
Structure for a duty cycle correction circuit |
David William Boerstler, Eskinder Hailu |
2013-02-19 |
$3,959,000 |
| 8201112 |
Structure for managing voltage swings across field effect transistors |
David William Boerstler |
2012-06-12 |
$5,600,000 |
| 8183920 |
Variable gain amplifier with reduced power consumption |
David William Boerstler, Minhan Chen, Hayden C. Cranford, Jr. |
2012-05-22 |
$8,891,000 |
| 8108813 |
Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler |
David William Boerstler, Eskinder Hailu, Masaaki Kaneko |
2012-01-31 |
$4,013,000 |
| 8054119 |
System and method for on/off-chip characterization of pulse-width limiter outputs |
David William Boerstler, Eskinder Hailu |
2011-11-08 |
$3,097,000 |
| 8041537 |
Clock duty cycle measurement with charge pump without using reference clock calibration |
Eskinder Hailu, David William Boerstler, Masaaki Kaneko |
2011-10-18 |
$4,054,000 |
| 8037431 |
Structure for interleaved voltage controlled oscillator |
David William Boerstler, Eskinder Hailu, Mike Shen |
2011-10-11 |
$5,277,000 |
| 8032850 |
Structure for an absolute duty cycle measurement circuit |
David William Boerstler, Eskinder Hailu, Masaaki Kaneko, Bin Wan |
2011-10-04 |
$5,606,000 |
| 7994830 |
Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction |
Masaaki Kaneko, David William Boerstler, Eskinder Hailu |
2011-08-09 |
$2,733,000 |
| 7969250 |
Structure for a programmable interpolative voltage controlled oscillator with adjustable range |
David William Boerstler, Eskinder Hailu, Masaaki Kaneko |
2011-06-28 |
$4,369,000 |
| 7958469 |
Design structure for a phase locked loop with stabilized dynamic response |
David William Boerstler, Eskinder Hailu |
2011-06-07 |
$3,978,000 |
| 7917795 |
Digital circuit to measure and/or correct duty cycles |
David William Boerstler, Eskinder Hailu, Byron L. Krauter, Kazuhiko Miki |
2011-03-29 |
$5,031,000 |
| 7917318 |
Structure for a duty cycle measurement circuit |
David William Boerstler, Eskinder Hailu, Masaaki Kaneko, Bin Wan |
2011-03-29 |
$5,031,000 |
