Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8830758 | Semiconductor storage device | Seiro Imai | 2014-09-09 |
| 8736304 | Self-biased high speed level shifter circuit | David William Boerstler, Eskinder Hailu, Jieming Qi | 2014-05-27 |
| 8278996 | Reference current generating circuit | Toru Takahashi | 2012-10-02 |
| 7917795 | Digital circuit to measure and/or correct duty cycles | David William Boerstler, Eskinder Hailu, Byron L. Krauter, Jieming Qi | 2011-03-29 |
| 7747892 | System for automatically selecting intermediate power supply voltages for intermediate level shifters | David William Boerstler, Eskinder Hailu, Jieming Qi | 2010-06-29 |
| 7724056 | Semiconductor integrated circuit device operating in synchronism with clock and method for controlling duty of clock | Yutaka Nakamura | 2010-05-25 |
| 7716516 | Method for controlling operation of microprocessor which performs duty cycle correction process | Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu +8 more | 2010-05-11 |
| 7519498 | Thermal sensing method and apparatus using existing ESD devices | David William Boerstler, Eskinder Hailu, Jieming Qi | 2009-04-14 |
| 7392419 | System and method automatically selecting intermediate power supply voltages for intermediate level shifters | David William Boerstler, Eskinder Hailu, Jieming Qi | 2008-06-24 |
| 7350095 | Digital circuit to measure and/or correct duty cycles | David William Boerstler, Eskinder Hailu, Byron L. Krauter, Jieming Qi | 2008-03-25 |
| 7265600 | Level shifter system and method to minimize duty cycle error due to voltage differences across power domains | David William Boerstler, Eskinder Hailu, Jieming Qi | 2007-09-04 |
| 7265634 | System and method for phase-locked loop initialization | — | 2007-09-04 |
| 7245172 | Level shifter apparatus and method for minimizing duty cycle distortion | David William Boerstler, Eskinder Hailu, Jieming Qi | 2007-07-17 |
| 7225092 | Method and apparatus for measuring and adjusting the duty cycle of a high speed clock | David William Boerstler, Eskinder Hailu | 2007-05-29 |
| 7205853 | Method to configure phase-locked loop dividing ratio | — | 2007-04-17 |
| 7176731 | Variation tolerant charge leakage correction circuit for phase locked loops | Franklin M. Baez, David William Boerstler, Eskinder Hailu | 2007-02-13 |
| 7171318 | PLL filter leakage sensor | David William Boerstler, Eskinder Hailu | 2007-01-30 |
| 7061223 | PLL manufacturing test apparatus | David William Boerstler | 2006-06-13 |
| 7019572 | Systems and methods for initializing PLLs and measuring VCO characteristics | David William Boerstler | 2006-03-28 |
| 6927635 | Lock detectors having a narrow sensitivity range | David William Boerstler | 2005-08-09 |
| 6021068 | Nonvolatile semiconductor memory with read circuit using flip-flop type sense amplifier | Hideo Sakai | 2000-02-01 |
| 5606524 | Non-volatile semiconductor memory device capable of effecting high-speed operation with low voltage | Kouji Ozaki | 1997-02-25 |
| 5270978 | Nonvolatile memory circuit | Osamu Matsumoto | 1993-12-14 |