Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10804919 | Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods | Michael R. Trombley | 2020-10-13 |
| 10447389 | Managing data flow in VCSEL-based optical communications system | Jonathan E. Proesel, Rashmi R. Bindu | 2019-10-15 |
| 10432209 | Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods | Steven E. Mikes, John K. Koehler, Steven J. Baumgartner | 2019-10-01 |
| 10396811 | Temperature compensation for reference voltages in an analog-to-digital converter | John Rankin, Stacy Garvin | 2019-08-27 |
| 10250010 | Control of VCSEL-based optical communications system | Rashmi R. Bindu, Jonathan E. Proesel | 2019-04-02 |
| 10211790 | Peaking amplifier frequency tuning | Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes | 2019-02-19 |
| 10075174 | Phase rotator apparatus | William L. Bucossi, Vivek K. Sharma, Fengqi Zhang | 2018-09-11 |
| 10033334 | Peaking amplifier frequency tuning | Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes | 2018-07-24 |
| 9960738 | Peaking amplifier frequency tuning | Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes | 2018-05-01 |
| 9853612 | Peaking amplifier frequency tuning | Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes | 2017-12-26 |
| 9571111 | System and method to speed up PLL lock time on subsequent calibrations via stored band values | Venkatasreekanth Prudvi, Rajesh Agraramachandrarao, Sandeep Niranjan Tippannanavar, Neelamekakannan Alagarsamy | 2017-02-14 |
| 9235543 | Systems for signal detection | Daniel M. Dreps, William R. Kelly | 2016-01-12 |
| 9231796 | Power aware equalization in a serial communications link | John F. Bulzacchelli, Daniel M. Dreps, David W. Siljenberg | 2016-01-05 |
| 9213667 | Systems and methods for signal detection | Daniel M. Dreps, William R. Kelly | 2015-12-15 |
| 9209948 | Testing a decision feedback equalizer (‘DFE’) | Eugene Atwood, Matthew B. Baecher, Minhan Chen, William R. Kelly, Todd M. Rasmus | 2015-12-08 |
| 9014254 | Testing a decision feedback equalizer (‘DFE’) | Eugene Atwood, Matthew B. Baecher, Minhan Chen, William R. Kelly, Todd M. Rasmus | 2015-04-21 |
| 8989313 | Adaptable receiver detection | John J. Bergkvist, Jr., Steven M. Clements, Carrie E. Cox, Todd E. Leonard | 2015-03-24 |
| 8798204 | Serial link receiver for handling high speed transmissions | Minhan Chen | 2014-08-05 |
| 8219041 | Design structure for transmitter bandwidth optimization circuit | Louis L. Hsu, Joseph Natonio, James D. Rockrohr, Huihao Xu, Steven J. Zier | 2012-07-10 |
| 8219040 | Transmitter bandwidth optimization circuit | Louis L. Hsu, Joseph Natonio, James D. Rockrohr, Huihao Xu, Steven J. Zier | 2012-07-10 |
| 8183920 | Variable gain amplifier with reduced power consumption | Jieming Qi, David William Boerstler, Minhan Chen | 2012-05-22 |
| 7995660 | Receiver termination circuit for a high speed direct current (DC) serial link | Carrie E. Cox | 2011-08-09 |
| 7983368 | Systems and arrangements for clock and data recovery in communications | Daniel J. Friedman, Mounir Meghelli, Thomas H. Toifl | 2011-07-19 |
| 7916820 | Systems and arrangements for clock and data recovery in communications | Daniel J. Friedman, Mounir Meghelli, Thomas H. Toifl | 2011-03-29 |
| 7769057 | High speed serial link output stage having self adaptation for various impairments | Steven M. Clements, Carrie E. Cox | 2010-08-03 |