Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9571111 | System and method to speed up PLL lock time on subsequent calibrations via stored band values | Hayden C. Cranford, Jr., Venkatasreekanth Prudvi, Rajesh Agraramachandrarao, Neelamekakannan Alagarsamy | 2017-02-14 |
| 8001503 | Method and system for automatically accessing internal signals or ports in a design hierarchy | Jayashri Arsikere Basappa, Venkatasreekanth Prudvi | 2011-08-16 |