Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9571111 | System and method to speed up PLL lock time on subsequent calibrations via stored band values | Hayden C. Cranford, Jr., Venkatasreekanth Prudvi, Rajesh Agraramachandrarao, Sandeep Niranjan Tippannanavar | 2017-02-14 |
| 7991819 | Binary coded decimal addition | Kulanthaivelu Veluchamy Balamurugan | 2011-08-02 |
| 7299254 | Binary coded decimal addition | Kulanthaivelu Veluchamy Balamurugan | 2007-11-20 |