Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12379695 | Time-to-digital converters (TDC) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (PLL) | Ping-Hung Lu | 2025-08-05 |
| 12362902 | Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods | Ping-Hung Lu | 2025-07-15 |
| 12216434 | Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods | Ping-Hung Lu | 2025-02-04 |
| 12212327 | Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods | Ping-Hung Lu, Bupesh Pandita | 2025-01-28 |
| 11953527 | Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods | Ping-Hung Lu, Shaishav Desai | 2024-04-09 |
| 11159151 | Calibrating a phase interpolator by amplifying timing differences | Ping-Hung Lu | 2021-10-26 |
| 10965442 | Low-power, low-latency time-to-digital-converter-based serial link | Eskinder Hailu, Bupesh Pandita, Jon Boyette, Hadi Goudarzi, Yong Suk Jun +1 more | 2021-03-30 |
| 10505705 | Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin | Li Sun, Chia Heng Chang, Hadi Goudarzi, Russell Coleman Deans | 2019-12-10 |
| 10326417 | Offset nulling for high-speed sense amplifier | Todd M. Rasmus | 2019-06-18 |
| 10079698 | Apparatus and method for calibrating a receiver with a decision feedback equalizer (DFE) | — | 2018-09-18 |
| 9722823 | Offset calibration for low power and high performance receiver | Kenneth Luis Arcudia | 2017-08-01 |
| 9614502 | Accurate sample latch offset compensation scheme | Kenneth Luis Arcudia | 2017-04-04 |
| 9444657 | Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations | Jieming Qi | 2016-09-13 |
| 9385695 | Offset calibration for low power and high performance receiver | Kenneth Luis Arcudia | 2016-07-05 |
| 9209948 | Testing a decision feedback equalizer (‘DFE’) | Eugene Atwood, Matthew B. Baecher, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus | 2015-12-08 |
| 9184948 | Decision feedback equalizer (‘DFE’) with a plurality of independently-controlled isolated power domains | Steven M. Clements, Carrie E. Cox, Todd M. Rasmus | 2015-11-10 |
| 9014254 | Testing a decision feedback equalizer (‘DFE’) | Eugene Atwood, Matthew B. Baecher, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus | 2015-04-21 |
| 8798204 | Serial link receiver for handling high speed transmissions | Hayden C. Cranford, Jr. | 2014-08-05 |
| 8183920 | Variable gain amplifier with reduced power consumption | Jieming Qi, David William Boerstler, Hayden C. Cranford, Jr. | 2012-05-22 |
| 7486114 | Signal detector with calibration circuit arrangement | Louis L. Hsu, Joseph Natonio, Karl D. Selander, Michael A. Sorna, Steven J. Zier | 2009-02-03 |
| 7268624 | Differential amplifier offset voltage minimization independently from common mode voltage adjustment | Westerfield J. Ficken, Louis L. Hsu, Steven J. Zier | 2007-09-11 |
| 6535043 | Clock signal selection system, method of generating a clock signal and programmable clock manager including same | — | 2003-03-18 |