Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12288581 | Efficient and low power reference voltage mixing | Karthik Gopalakrishnan, Ramon Mangaser | 2025-04-29 |
| 12154656 | Error pin training with graphics DDR memory | Karthik Gopalakrishnan, Pradeep Jayaraman | 2024-11-26 |
| 12093124 | Multi-level signal reception | Karthik Gopalakrishnan, Pradeep Jayaraman, Ramon Mangaser | 2024-09-17 |
| 12019876 | Feed forward training of memory interfaces | Karthik Gopalakrishnan, Pradeep Jayaraman | 2024-06-25 |
| 11996848 | Compensation for clock frequency modulation | Karthik Gopalakrishnan | 2024-05-28 |
| 11803437 | Write hardware training acceleration | Karthik Gopalakrishnan | 2023-10-31 |
| 11483185 | Hardware efficient decision feedback equalization training | Sachin Ramesh Gugwad, Hari Anand Ravi, Thomas Evan Wilson | 2022-10-25 |
| 10848352 | Time based feed forward equalization (TFFE) for high-speed DDR transmitter | Balbeer Singh Rathor, Vinod Kumar | 2020-11-24 |
| 10705984 | High-speed low VT drift receiver | H Md Shuaeb Fazeel, Nikhil Sawarkar, Thomas Evan Wilson | 2020-07-07 |
| 10608648 | Single-lock delay locked loop with cycle counter and method therefor | Jieming Qi | 2020-03-31 |
| 10545895 | Auto-zeroing receiver for memory interface devices | Hari Anand Ravi, H. Md. Shuaeb Fazeel, Thomas Evan Wilson, Moo Sung Chae | 2020-01-28 |
| 10545889 | High-speed low VT drift receiver | H Md Shuaeb Fazeel, Nikhil Sawarkar, Thomas Evan Wilson | 2020-01-28 |
| 10250265 | Single-lock delay locked loop with cycle counter and method therefor | Jieming Qi | 2019-04-02 |
| 10056909 | Single-lock delay locked loop with cycle counter and method therefore | Jieming Qi | 2018-08-21 |
| 9899087 | Content addressable dynamic random-access memory with parallel search functionality | Wolfgang Hokenmaier, Ryan Andrew Jurasek, Donald W. Labrecque | 2018-02-20 |
| 9419628 | Measurement initialization circuitry | Yantao Ma | 2016-08-16 |
| 9244479 | Current generator circuit and methods for providing an output current | — | 2016-01-26 |
| 9225319 | Apparatus and methods for altering the timing of a clock signal | Yantao Ma | 2015-12-29 |
| 9202542 | Power supply induced signal jitter compensation | Yantao Ma | 2015-12-01 |
| 9036408 | Phase change memory with bit line matching | Ryan Andrew Jurasek | 2015-05-19 |
| 8947141 | Differential amplifiers, clock generator circuits, delay lines and methods | — | 2015-02-03 |
| 8908427 | Phase change memory with flexible time-based cell decoding | Ryan Andrew Jurasek | 2014-12-09 |
| 8901938 | Delay line scheme with no exit tree | Yantao Ma | 2014-12-02 |
| 8897063 | Multilevel differential sensing in phase change memory | Ryan Andrew Jurasek | 2014-11-25 |
| 8891294 | Multilevel differential sensing in phase change memory | Ryan Andrew Jurasek | 2014-11-18 |