BR

Balbeer Singh Rathor

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
📍 Morena, IN: #1 of 2 inventorsTop 50%
Overall (All Time): #1,123,465 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
11580048 Reference voltage training scheme Thomas Evan Wilson, Scott David Huss, Hari Anand Ravi, Sachin Ramesh Gugwad 2023-02-14
11082267 Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter Vinod Kumar, Harsh Anil Shakrani 2021-08-03
10848352 Time based feed forward equalization (TFFE) for high-speed DDR transmitter Vinod Kumar, Aaron Willey 2020-11-24
9767888 Methods and devices for high-sensitivity memory interface receiver Hari Anand Ravi, Thomas Evan Wilson 2017-09-19