Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12205673 | Read data strobe path having variation compensation and delay lines | Hari Anand Ravi, Sachin Ramesh Gugwad, Jitendra Kumar Yadav, Vinod Kumar | 2025-01-21 |
| 11876521 | Dynamically updated delay line | Hajee Mohammed Shuaeb Fazeel, Jitendra Kumar Yadav | 2024-01-16 |
| 11677593 | Sampler with built-in DFE and offset cancellation | Vinod Kumar | 2023-06-13 |
| 11580048 | Reference voltage training scheme | Scott David Huss, Hari Anand Ravi, Sachin Ramesh Gugwad, Balbeer Singh Rathor | 2023-02-14 |
| 11545968 | Active suppression circuitry | Moo Sung Chae | 2023-01-03 |
| 11481148 | Slew rate boosting for communication interfaces | Vinod Kumar, Hajee Mohammed Shuaeb Fazeel | 2022-10-25 |
| 11483185 | Hardware efficient decision feedback equalization training | Sachin Ramesh Gugwad, Hari Anand Ravi, Aaron Willey | 2022-10-25 |
| 11323296 | Decision feedback equalization training scheme for GDDR applications | Sachin Ramesh Gugwad, Hari Anand Ravi, Vinod Kumar | 2022-05-03 |
| 10958484 | Time-based decision feedback equalizer | Hajee Mohammed Shuaeb Fazeel, Raksha | 2021-03-23 |
| 10705984 | High-speed low VT drift receiver | H Md Shuaeb Fazeel, Nikhil Sawarkar, Aaron Willey | 2020-07-07 |
| 10566046 | Protocol compliant high-speed DDR transmitter | Vinod Kumar, Hari Anand Ravi | 2020-02-18 |
| 10545889 | High-speed low VT drift receiver | H Md Shuaeb Fazeel, Nikhil Sawarkar, Aaron Willey | 2020-01-28 |
| 10545895 | Auto-zeroing receiver for memory interface devices | Aaron Willey, Hari Anand Ravi, H. Md. Shuaeb Fazeel, Moo Sung Chae | 2020-01-28 |
| 10389368 | Dual path phase-locked loop circuit | Fuyue Wang, Ling Chen, Jianyun Zhang, Eric Naviasky | 2019-08-20 |
| 10345845 | Fast settling bias circuit | Ling Chen, Fuyue Wang, Jianyun Zhang, Eric Naviasky | 2019-07-09 |
| 10193555 | Methods and devices for a memory interface receiver | Eric Naviasky | 2019-01-29 |
| 10161974 | Frequency to current circuit | Ling Chen, Fuyue Wang, Jianyun Zhang, Eric Naviasky | 2018-12-25 |
| 10128965 | Coupled inverter with auto-calibration | Moo Sung Chae | 2018-11-13 |
| 9767888 | Methods and devices for high-sensitivity memory interface receiver | Hari Anand Ravi, Balbeer Singh Rathor | 2017-09-19 |
| 9754646 | Voltage stress tolerant high speed memory driver having flying capacitor circuit | Vinod Kumar, Tara Vishin, Sachin Ramesh Gugwad | 2017-09-05 |
| 9589627 | Methods and devices for a DDR memory driver using a voltage translation capacitor | Eric Naviasky | 2017-03-07 |
| 9405314 | System and method for synchronously adjusted delay and distortion mitigated recovery of signals | Eric Naviasky | 2016-08-02 |
| 8910100 | System and method for automatically reconfiguring chain of abutted devices in electronic circuit design | Arnold Ginetti, Kenneth Ferguson, Yuan-Kai Pei | 2014-12-09 |
| 8737491 | Analog-to-digital converter based decision feedback equalization | Eric Naviasky | 2014-05-27 |
| 8737490 | Analog-to-digital converter based decision feedback equalization | Eric Naviasky | 2014-05-27 |