JY

Jitendra Kumar Yadav

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
VE Verizon: 2 patents #2,187 of 6,226Top 40%
AM AMD: 1 patents #5,683 of 9,279Top 65%
CI Ciena: 1 patents #757 of 1,406Top 55%
Overall (All Time): #530,559 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
12425032 Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture Prakash Kumar Lenka, Sumit Gupta, Vinod Kumar, Virvasav Sinha, Rajashekhar Rao 2025-09-23
12413213 Efficient clocking structures for high-speed systems using hybrid digital delay lanes Sachin Ramesh Gugwad, Hari Anand Ravi, Hajee Mohammed Shuaeb Fazeel 2025-09-09
12205673 Read data strobe path having variation compensation and delay lines Hari Anand Ravi, Sachin Ramesh Gugwad, Thomas Evan Wilson, Vinod Kumar 2025-01-21
12184286 Clock duty cycle measurement Prakash Kumar Lenka, Hari Anand Ravi 2024-12-31
12081407 Updating configuration settings of network elements when a network is changed to a planned topology Dale Frederick Zacharias 2024-09-03
11876521 Dynamically updated delay line Hajee Mohammed Shuaeb Fazeel, Thomas Evan Wilson 2024-01-16
11005973 Automatic bootstrapping and dynamic configuration of data center nodes Manish Chugtu, Sivaram Subramaniyan Kannan, Vishant Singh 2021-05-11
10979034 Method and apparatus for multi-voltage domain sequential elements Kumar Rahul, Santosh Yachareni, Md Nadeem Iqbal, Teja Masina, Sourabh Swarnkar +1 more 2021-04-13
10516760 Automatic bootstrapping and dynamic configuration of data center nodes Manish Chugtu, Sivaram Subramaniyan Kannan, Vishant Singh 2019-12-24