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Last level cache hierarchy in chiplet based processors |
Srikanth Reddy Gruddanti, Krishnaiah Gummidipudi, Prasant Kumar Vallur, David Hugh McIntyre |
2025-08-12 |
| 12321294 |
Data lane variation compensation for data rate enhancement |
Srikanth Reddy Gruddanti, David Hugh McIntyre, Prasant Kumar Vallur, Manoj N. Kulkarni |
2025-06-03 |
| 12288581 |
Efficient and low power reference voltage mixing |
Aaron Willey, Karthik Gopalakrishnan |
2025-04-29 |
| 12101135 |
Noise mitigation in single-ended links |
Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman |
2024-09-24 |
| 12093124 |
Multi-level signal reception |
Aaron Willey, Karthik Gopalakrishnan, Pradeep Jayaraman |
2024-09-17 |
| 12088296 |
Clock gating using a cascaded clock gating control signal |
Srikanth Reddy Gruddanti, Prasant Kumar Vallur, Krishna Reddy Mudimela Venkata, Oikwan Tsang |
2024-09-10 |
| 12015412 |
Dual phase clock distribution from a single source in a die-to-die interface |
Srikanth Reddy Gruddanti, Pradeep Jayaraman, Prasant Kumar Vallur, Krishna Reddy Mudimela Venkata, David Hugh McIntyre |
2024-06-18 |
| 11960435 |
Skew matching in a die-to-die interface |
Pradeep Jayaraman, Dean E. Gonzales, Gerald R. Talbot, Michael J. Tresidder, Prasant Kumar Vallur +3 more |
2024-04-16 |
| 11757489 |
Noise mitigation in single ended links |
Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman |
2023-09-12 |
| 8553754 |
Method and apparatus for using DFE in a system with non-continuous data |
Shefali Walia, Edoardo Prete, Jonathan P. Dowling, Gerald R. Talbot, Sharad N. Vittal |
2013-10-08 |