Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373369 | Scheduling training of an inter-chiplet interface | Benjamin Tsien | 2025-07-29 |
| 12174775 | Apparatuses, systems, and methods for multi-lane data bus inversion | Padmini Nujetti, Chao Yu, Daniel McLean | 2024-12-24 |
| 12147366 | Droop mitigation for an inter-chiplet interface | Benjamin Tsien | 2024-11-19 |
| 12052153 | Dynamic fine grain link control | Alexander J. Branover, Thomas J. Gibney, Nat Barbiero | 2024-07-30 |
| 11960435 | Skew matching in a die-to-die interface | Pradeep Jayaraman, Dean E. Gonzales, Gerald R. Talbot, Ramon Mangaser, Prasant Kumar Vallur +3 more | 2024-04-16 |
| 11693465 | Method and apparatus for data scrambling | Yanfeng Wang, Kevin M. Lepak, Larry D. Hewitt, Noah Beck | 2023-07-04 |
| 11281280 | Reducing chiplet wakeup latency | Benjamin Tsien, Ivan Yanfeng Wang, Kevin M. Lepak, Ann Ling, Richard Martin Born +3 more | 2022-03-22 |
| 11283589 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi +6 more | 2022-03-22 |
| 11132327 | Method and apparatus for physical layer bypass | Yanfeng Wang, Shiqi Sun | 2021-09-28 |
| 10895901 | Method and apparatus for data scrambling | Yanfeng Wang, Kevin M. Lepak, Larry D. Hewitt, Noah Beck | 2021-01-19 |
| 10873445 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi +6 more | 2020-12-22 |
| 10656696 | Reducing chiplet wakeup latency | Benjamin Tsien, Ivan Yanfeng Wang, Kevin M. Lepak, Ann Ling, Richard Martin Born +3 more | 2020-05-19 |
| 10581587 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi +6 more | 2020-03-03 |
| 10541841 | Hardware transmit equalization for high speed | Shiqi Sun, Yanfeng Wang | 2020-01-21 |
| 9621143 | Propagation simulation buffer for clock domain crossing | Michael J. Osborn, Aaron Joseph Grenat, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch | 2017-04-11 |
| 9569395 | Fast exit from low-power state for bus protocol compatible device | — | 2017-02-14 |
| 9117036 | Fast exit from low-power state for bus protocol compatible device | — | 2015-08-25 |
| 9069466 | Methods and apparatus for source-synchronous circuits | Li-Hsiang Sun | 2015-06-30 |
| 8879680 | Adaptive clock mismatch compensation symbol insertion in signal transmissions | Gordon Caruk | 2014-11-04 |
| 8868945 | Device having multiple graphics subsystems and reduced power consumption mode, software and methods | Sasa Marinkovic, Phil Mummah, Mingwei Chien, Roumen Saltchev, George Xie +1 more | 2014-10-21 |
| 8584067 | Clock domain crossing buffer | Michael J. Osborn, Aaron Joseph Grenat, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch | 2013-11-12 |
| 8555099 | Device having multiple graphics subsystems and reduced power consumption mode, software and methods | Sasa Marinkovic, Phil Mummah, Mingwei Chien, Roumen Saltchev, George Xie +1 more | 2013-10-08 |
| 7730336 | Device having multiple graphics subsystems and reduced power consumption mode, software and methods | Sasa Marinkovic, Phil Mummah, Mingwei Chien, Roumen Saltchev, George Xie +1 more | 2010-06-01 |
| 6353906 | Testing synchronization circuitry using digital simulation | Michael B. Smith | 2002-03-05 |
| 6081527 | Asynchronous transfer scheme using multiple channels | John Fraser Chappel | 2000-06-27 |