Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388490 | Receiver equalization circuitry using variable termination and T-coil | Dean E. Gonzales, Edoardo Prete, Milam Paraschou, Mark Chirachanchai | 2025-08-12 |
| 12287753 | Alternative protocol over physical layer | Gordon Caruk, Maurice B. Steinman, Joseph Macri | 2025-04-29 |
| 12174769 | Periodic receiver clock data recovery with dynamic data edge | Gurunath Dollin, Edoardo Prete, Milam Paraschou, Edward Wade Thoenes, Ryan J. Hensley | 2024-12-24 |
| 12034440 | Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links | Rajesh Kumar, Edoardo Prete, Ethan Crain, Tracy J. Feist, Jeffrey Cooper | 2024-07-09 |
| 11960435 | Skew matching in a die-to-die interface | Pradeep Jayaraman, Dean E. Gonzales, Ramon Mangaser, Michael J. Tresidder, Prasant Kumar Vallur +3 more | 2024-04-16 |
| 11805026 | Channel training using a replica lane | Stanley A. Lackey, Jr., Damon Tohidi, Edoardo Prete | 2023-10-31 |
| 11693813 | Alternative protocol over physical layer | Gordon Caruk, Maurice B. Steinman, Joseph Macri | 2023-07-04 |
| 11283589 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter +6 more | 2022-03-22 |
| 11151075 | Data communications with enhanced speed mode | Gordon Caruk | 2021-10-19 |
| 10873445 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter +6 more | 2020-12-22 |
| 10749756 | Channel training using a replica lane | Stanley A. Lackey, Jr., Damon Tohidi, Edoardo Prete | 2020-08-18 |
| 10749552 | Pseudo differential receiving mechanism for single-ended signaling | Balwinder Singh, Milam Paraschou, Chad S. Gallun, Jeffrey Cooper, Dean E. Gonzales +2 more | 2020-08-18 |
| 10698856 | Alternative protocol selection | Gordon Caruk | 2020-06-30 |
| 10692545 | Low power VTT generation mechanism for receiver termination | Milam Paraschou, Balwinder Singh, Alushulla Jack Ambundo, Edoardo Prete, Thomas H. Likens, III +1 more | 2020-06-23 |
| 10636736 | Land pad design for high speed terminals | Sanjay Dandia, Mahesh S. Hardikar | 2020-04-28 |
| 10581587 | Deskewing method for a physical layer interface on a multi-chip module | Varun Gupta, Milam Paraschou, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter +6 more | 2020-03-03 |
| 10122392 | Active equalizing negative resistance amplifier for bi-directional bandwidth extension | Milam Paraschou, Dean E. Gonzales | 2018-11-06 |
| 10103837 | Asynchronous feedback training | Stanley A. Lackey, Jr., Damon Tohidi, Edoardo Prete | 2018-10-16 |
| 9374080 | Method and apparatus for power-up detection for an electrical monitoring circuit | Brian Amick, Warren Anderson | 2016-06-21 |
| 9214199 | DDR 2D Vref training | Kevin M. Brandl, Oswin E. Housty | 2015-12-15 |
| 9213355 | Selective insertion of clock mismatch compensation symbols in signal transmissions based on a receiver's compensation capability | Gordon Caruk | 2015-12-15 |
| 9183125 | DDR receiver enable cycle training | Kevin M. Brandl, Oswin E. Housty, Edoardo Prete | 2015-11-10 |
| 8850155 | DDR 2D Vref training | Kevin M. Brandl, Oswin E. Housty | 2014-09-30 |
| 8760946 | Method and apparatus for memory access delay training | Glenn Dearth, Warren Anderson, Anwar Kashem, Richard W. Reeves, Edoardo Prete | 2014-06-24 |
| 8570881 | Transmitter voltage and receiver time margining | Paul C. Miranda, Emerson S. Fang, Rohit Kumar | 2013-10-29 |