KB

Kevin M. Brandl

AM AMD: 29 patents #329 of 9,279Top 4%
Overall (All Time): #127,387 of 4,157,543Top 4%
29
Patents All Time

Issued Patents All Time

Showing 25 most recent of 29 patents

Patent #TitleCo-InventorsDate
12333158 Efficient memory power control operations Jean J. Chittilappilly, Michael L. Choate 2025-06-17
12322434 Directed refresh management for DRAM James R. Magro, Kedarnath Balakrishnan, Jing Wang 2025-06-03
12299297 Memory controller with enhanced low-power state Jean J. Chittilappilly, Tahsin Askar, James R. Magro 2025-05-13
12265732 Refresh during power state changes Jean J. Chittilappilly, Jing Wang, Kedarnath Balakrishnan 2025-04-01
12243576 Memory calibration system and method Jing Wang, Kedarnath Balakrishnan, James R. Magro 2025-03-04
12158827 Full dynamic post-package repair Kedarnath Balakrishnan, James R. Magro 2024-12-03
11809743 Refresh management list for DRAM 2023-11-07
11694739 Refresh management for memory Kedarnath Balakrishnan, Jing Wang, Guanhao Shen 2023-07-04
11682445 Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training Naveen Davanam, Oswin E. Housty 2023-06-20
11664062 Memory calibration system and method Jing Wang, Kedarnath Balakrishnan, James R. Magro 2023-05-30
11636054 Memory controller power states Indrani Paul, Jean J. Chittilappilly, Abhishek Kumar Verma, James R. Magro, Kavyashree Pilar 2023-04-25
11526278 Adaptive page close prediction Guanhao Shen, Ravindra N. Bhargava, James R. Magro, Kedarnath Balakrishnan 2022-12-13
11474746 Refresh management for DRAM 2022-10-18
11221772 Self refresh state machine mop array Thomas H. Hamilton 2022-01-11
11222685 Refresh management for DRAM Kedarnath Balakrishnan, Jing Wang, Guanhao Shen 2022-01-11
11176986 Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training Naveen Davanam, Oswin E. Housty 2021-11-16
10572183 Power efficient retraining of memory accesses Sonu Arora, Guhan Krishnan 2020-02-25
10403333 Memory controller with flexible address decoding Thomas H. Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen +1 more 2019-09-03
10198216 Low power memory throttling Kedarnath Balakrishnan, James R. Magro 2019-02-05
10198204 Self refresh state machine MOP array Thomas H. Hamilton 2019-02-05
10067718 Multi-purpose register pages for read training Glennis Eliagh Covington, Nienchi Hu, Shannon T. Kesner 2018-09-04
10042700 Integral post package repair 2018-08-07
9965222 Software mode register access for platform margining and debug Scott P. Murphy, James R. Magro, Paramjit K. Lubana 2018-05-08
9293188 Memory and memory controller for high reliability operation and method 2016-03-22
9281046 Data processor with memory controller for high reliability operation and method 2016-03-08