Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11682445 | Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training | Kevin M. Brandl, Naveen Davanam | 2023-06-20 |
| 11176986 | Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training | Kevin M. Brandl, Naveen Davanam | 2021-11-16 |
| 10311236 | Secure system memory training | Kathirkamanathan Nadarajah, Sergey Blotsky, Tan Peng, Hary Devapriyan Mahesan | 2019-06-04 |
| 9214199 | DDR 2D Vref training | Kevin M. Brandl, Gerald R. Talbot | 2015-12-15 |
| 9183125 | DDR receiver enable cycle training | Kevin M. Brandl, Edoardo Prete, Gerald R. Talbot | 2015-11-10 |
| 8850155 | DDR 2D Vref training | Kevin M. Brandl, Gerald R. Talbot | 2014-09-30 |
| 8566570 | Distributed multi-core memory initialization | — | 2013-10-22 |
| 8392640 | Pre-memory resource contention resolution | — | 2013-03-05 |
| 8307198 | Distributed multi-core memory initialization | — | 2012-11-06 |
| 8176303 | Multiprocessor communication device and methods thereof | Bernucho S Krishna | 2012-05-08 |
| 8055939 | Memory control device and methods thereof | David M. Lynch, Andelon Xuan Tra | 2011-11-08 |
| 7971098 | Bootstrap device and methods thereof | Andelon Xuan Tra, David M. Lynch | 2011-06-28 |
| 7924637 | Method for training dynamic random access memory (DRAM) controller timing delays | Shawn Searles, Tahsin Askar, Thomas H. Hamilton | 2011-04-12 |
| 7251744 | Memory check architecture and method for a multiprocessor computer system | — | 2007-07-31 |