TA

Tahsin Askar

AM AMD: 18 patents #607 of 9,279Top 7%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Overall (All Time): #229,883 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12299297 Memory controller with enhanced low-power state Kevin M. Brandl, Jean J. Chittilappilly, James R. Magro 2025-05-13
11340786 Apparatus and methods for synchronizing a plurality of double data rate memory ranks 2022-05-24
9122648 Temperature throttling mechanism for DDR3 memory Philip E. Madrid 2015-09-01
8607104 Memory diagnostics system and method with hardware-based read/write patterns Hanwoo Cho, Philip E. Madrid, Guhan Krishnan, Brian Amick, Shawn Searles +1 more 2013-12-10
8006032 Optimal solution to control data channels Philip E. Madrid 2011-08-23
7924637 Method for training dynamic random access memory (DRAM) controller timing delays Shawn Searles, Thomas H. Hamilton, Oswin E. Housty 2011-04-12
7761656 Detection of speculative precharge Philip E. Madrid 2010-07-20
6996657 Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system Eric G. Chambers 2006-02-07
6968417 Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system Eric G. Chambers 2005-11-22
6883045 Apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system Eric G. Chambers 2005-04-19
6834314 Method and apparatus for reordering packet transactions within a peripheral interface circuit 2004-12-21
6823405 Method and apparatus for initiating partial transactions in a peripheral interface circuit for an I/O node of a computer system 2004-11-23
6760791 Buffer circuit for a peripheral interface circuit in an I/O node of a computer system 2004-07-06
6760792 Buffer circuit for rotating outstanding transactions 2004-07-06
6757755 Peripheral interface circuit for handling graphics responses in an I/O node of a computer system James R. Magro 2004-06-29
6725297 Peripheral interface circuit for an I/O node of a computer system Larry D. Hewitt, Eric G. Chambers 2004-04-20
6173243 Memory incoherent verification methodology Mike Lowe, Mark Gerald LaVine, Jelena Ilic, Paul W. Berndt, Enrique Rendon +1 more 2001-01-09
6154801 Verification strategy using external behavior modeling Mike Lowe, Mark Gerald LaVine, Jelena Ilic, Paul W. Berndt, Enrique Rendon +1 more 2000-11-28
6081864 Dynamic configuration of a device under test Mike Lowe, Paul W. Berndt, Enrique Rendon 2000-06-27