Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11379157 | Dynamic random access memory (DRAM) bandwidth increase without per pin bandwidth increase | — | 2022-07-05 |
| 9122648 | Temperature throttling mechanism for DDR3 memory | Tahsin Askar | 2015-09-01 |
| 8607104 | Memory diagnostics system and method with hardware-based read/write patterns | Hanwoo Cho, Tahsin Askar, Guhan Krishnan, Brian Amick, Shawn Searles +1 more | 2013-12-10 |
| 8594966 | Data processing interface device | Stephen C. Ennis | 2013-11-26 |
| 8195849 | Device and method for transferring data between devices | Wade Williams | 2012-06-05 |
| 8006032 | Optimal solution to control data channels | Tahsin Askar | 2011-08-23 |
| 7996653 | Shared resources in a chip multiprocessor | William A. Hughes, Vydhyanathan Kalyanasundharam, Kiran Bondalapati, Stephen C. Ennis | 2011-08-09 |
| 7877558 | Memory controller prioritization scheme | William A. Hughes, Vydhyanathan Kalyanasundharam, Roger D. Isaac | 2011-01-25 |
| 7840780 | Shared resources in a chip multiprocessor | William A. Hughes, Vydhyanathan Kalyanasundharam, Kiran Bondalapati, Stephen C. Ennis | 2010-11-23 |
| 7761656 | Detection of speculative precharge | Tahsin Askar | 2010-07-20 |
| 7636803 | Device and method for transferring data between devices | Wade Williams | 2009-12-22 |
| 7607061 | Shrink test mode to identify Nth order speed paths | Michael A. Comai | 2009-10-20 |
| 7383423 | Shared resources in a chip multiprocessor | William A. Hughes, Vydhyanathan Kalyanasundharam, Kiran Bondalapati, Stephen C. Ennis | 2008-06-03 |
| 7328371 | Core redundancy in a chip multiprocessor for highly reliable systems | Vydhyanathan Kalyanasundharam, William A. Hughes, Scott White, Ajay Naini | 2008-02-05 |
| 7271634 | Delay-locked loop having a plurality of lock modes | Anand Daga, Sanjay Sethi | 2007-09-18 |
| 7263457 | System and method for operating components of an integrated circuit at independent frequencies and/or voltages | Scott White, William A. Hughes | 2007-08-28 |
| 6988217 | Method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency | Derrick R. Meyer | 2006-01-17 |
| 6976122 | Dynamic idle counter threshold value for use in memory paging policy | Benjamin T. Sander, Gregory W. Smaus | 2005-12-13 |
| 6760855 | System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay | William McGee | 2004-07-06 |
| 6668292 | System and method for initiating a serial data transfer between two clock domains | Derrick R. Meyer | 2003-12-23 |
| 6584575 | System and method for initializing source-synchronous data transfers using ratio bits | Deriick R. Meyer | 2003-06-24 |
| 6505261 | System and method for initiating an operating frequency using dual-use signal lines | Derrick R. Meyer | 2003-01-07 |
| 6446215 | Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface | Derrick R. Meyer, Scott White, Michael T. Clark | 2002-09-03 |
| 6393502 | System and method for initiating a serial data transfer between two clock domains | Derrick R. Meyer | 2002-05-21 |
| 5732381 | Method and system for generating a fuel pulse waveform | Samuel J. Guido, Rollie M. Fisher, John Mark Wilson, Micah C. Knapp, Gary Lynn Miller | 1998-03-24 |