Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11868818 | Lock address contention predictor | John M. King, Matthew A. Rafacz, Matthew M. Crum | 2024-01-09 |
| 11768771 | Techniques for handling cache coherency traffic for contended semaphores | John M. King | 2023-09-26 |
| 11379234 | Store-to-load forwarding | Francesco Spadini, Matthew A. Rafacz, Michael Achenbach, Christopher J. Burke, Emil Talpes +1 more | 2022-07-05 |
| 11216378 | Techniques for handling cache coherency traffic for contended semaphores | John M. King | 2022-01-04 |
| 11175916 | System and method for a lightweight fencing operation | John M. King | 2021-11-16 |
| 11036505 | Store-to-load forwarding | Francesco Spadini, Matthew A. Rafacz, Michael Achenbach, Christopher J. Burke, Emil Talpes +1 more | 2021-06-15 |
| 10095637 | Speculative retirement of post-lock instructions | John M. King, Michael Achenbach, Kevin M. Lepak, Matthew A. Rafacz, Noah Bamford | 2018-10-09 |
| 9727340 | Hybrid tag scheduler to broadcast scheduler entry tags for picked instructions | Michael Achenbach, Teik-Chung Tan, Ganesh Venkataramanan, Emil Talpes | 2017-08-08 |
| 9606806 | Dependence-based replay suppression | Michael Achenbach, Christopher J. Burke, Francesco Spadini | 2017-03-28 |
| 9582286 | Register file management for operations using a single physical register for both source and result | Ganesh Venkataramanan, Debjit Das Sarma, Betty A. McDaniel, Francesco Spadini | 2017-02-28 |
| 8069336 | Transitioning from instruction cache to trace cache on label boundaries | Mitchell Alsup | 2011-11-29 |
| 7694110 | System and method of implementing microcode operations as subroutines | Mitchell Alsup | 2010-04-06 |
| 7685406 | Determination of current stack pointer value using architectural and speculative stack pointer delta values | Christopher B. Svec, Faisal A. Syed, Michael E. Tuuk, Benjamin T. Sander | 2010-03-23 |
| 7610476 | Multiple control sequences per row of microcode ROM | Teik-Chung Tan | 2009-10-27 |
| 7555633 | Instruction cache prefetch based on trace cache eviction | Mitchell Alsup | 2009-06-30 |
| 7213126 | Method and processor including logic for storing traces within a trace cache | Raghuram S. Tupuri, Gerald D. Zuraski, Jr. | 2007-05-01 |
| 7133969 | System and method for handling exceptional instructions in a trace cache based processor | Mitchell Alsup, James K. Pickett, Brian D. McMinn, Michael Filippo, Benjamin T. Sander | 2006-11-07 |
| 6976122 | Dynamic idle counter threshold value for use in memory paging policy | Benjamin T. Sander, Philip E. Madrid | 2005-12-13 |