BM

Brian D. McMinn

AM AMD: 36 patents #243 of 9,279Top 3%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Overall (All Time): #90,856 of 4,157,543Top 3%
37
Patents All Time

Issued Patents All Time

Showing 25 most recent of 37 patents

Patent #TitleCo-InventorsDate
8010920 Constraint management and validation for template-based circuit design Richard L. Bartolotti, Thomas D. Burd, William McGee, Arun Chandra 2011-08-30
7937569 System and method for scheduling operations using speculative data operands Benjamin T. Sander 2011-05-03
7827355 Data processor having a cache with efficient storage of predecode information, cache, and method Karthikeyan Muthusamy 2010-11-02
7315935 Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots Mitchell Alsup, Benjamin T. Sander, David E. Kroesche 2008-01-01
7133969 System and method for handling exceptional instructions in a trace cache based processor Mitchell Alsup, Gregory W. Smaus, James K. Pickett, Michael Filippo, Benjamin T. Sander 2006-11-07
7127573 Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions Geoffrey S. Strongin, Dale E. Gulick 2006-10-24
7080170 Circular buffer using age vectors Gerald D. Zuraski, Jr., Michael Kevin Ciraula 2006-07-18
7069411 Mapper circuit with backup capability Mitchell Alsup 2006-06-27
7043626 Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming James K. Pickett, Mitchell Alsup 2006-05-09
6957319 Integrated circuit with multiple microcode ROMs James K. Pickett 2005-10-18
6873184 Circular buffer using grouping for find first function Michael Kevin Ciraula, Gerald D. Zuraski, Jr. 2005-03-29
6782486 Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer Paul C. Miranda 2004-08-24
6760392 Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios Teik-Chung Tan 2004-07-06
6711696 Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer Michael Bates 2004-03-23
6597620 Storage circuit with data retention during power down 2003-07-22
6539470 Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same Eric W. Mahurin 2003-03-25
6424688 Method to transfer data in a system with multiple clock domains using clock skipping techniques Teik-Chung Tan, Derrick R. Meyer 2002-07-23
6298424 Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation W. Kurt Lewchuk, James K. Pickett 2001-10-02
6219760 Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line 2001-04-17
6151662 Data transaction typing for improved caching and prefetching characteristics David S. Christie, Stephan G. Meier, James K. Pickett 2000-11-21
6138213 Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line 2000-10-24
6097403 Memory including logic for operating upon graphics primitives 2000-08-01
6058461 Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation W. Kurt Lewchuk, James K. Pickett 2000-05-02
6032252 Apparatus and method for efficient loop control in a superscalar microprocessor Anthony M. Petro 2000-02-29
5926646 Context-dependent memory-mapped registers for transparent expansion of a register file James K. Pickett, Rupaka Mahalingaiah 1999-07-20