Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11361819 | Staged bitline precharge | Andrew J. Robison, Eric Busta, Carson D. Henrion | 2022-06-14 |
| 10644826 | Flexibile interfaces using through-silicon via technology | John Wuu, Samuel D. Naffziger, Russell Schreiber | 2020-05-05 |
| 10509752 | Configuration of multi-die modules with through-silicon vias | Russell Schreiber, John Wuu, Patrick J. Shyvers | 2019-12-17 |
| 10452505 | Error injection for assessment of error detection and correction techniques using error injection logic and non-volatile memory | — | 2019-10-22 |
| 10303398 | Swizzling in 3D stacked memory | John Wuu, Russell Schreiber, Samuel D. Naffziger | 2019-05-28 |
| 9916246 | Predictive multistage comparison for associative memory | Carson D. Henrion, Gregg Donley, Alok Garg, Eric Busta | 2018-03-13 |
| 8533396 | Memory elements for performing an allocation operation and related methods | Carson D. Henrion, Ryan T. Freese | 2013-09-10 |
| 7417449 | Wafer stage storage structure speed testing | Randal L. Posey | 2008-08-26 |
| 7366032 | Multi-ported register cell with randomly accessible history | Jan-Michael Huber, Jerry D. Moench | 2008-04-29 |
| 7355881 | Memory array with global bitline domino read/write scheme | Floyd L. Dankert, Victor F. Andrade, Randal L. Posey, Alexander W. Schaefer, Jerry D. Moench +4 more | 2008-04-08 |
| 7080170 | Circular buffer using age vectors | Gerald D. Zuraski, Jr., Brian D. McMinn | 2006-07-18 |
| 6873184 | Circular buffer using grouping for find first function | Brian D. McMinn, Gerald D. Zuraski, Jr. | 2005-03-29 |
| 6150834 | Elimination of SOI parasitic bipolar effect | Christopher McCall Durham, Peter Juergen Klim | 2000-11-21 |
| 6121796 | Power-saving dynamic circuit | Donald George Mikan, Jr. | 2000-09-19 |
| 6111434 | Circuit having anti-charge share characteristics and method therefore | David James Martens, Robert P. Masleid | 2000-08-29 |
| 6108255 | Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry | George McNeil Lattimore, Gus Yeung | 2000-08-22 |
| 6094071 | Initialization of floating body dynamic circuitry | Visweswara Rao Kodali | 2000-07-25 |
| 6085289 | Method and system for load data formatting and improved method for cache line organization | Larry Edward Thatcher, John Andrew Beck | 2000-07-04 |
| 6064616 | Conditional restore for SRAM | George McNeil Lattimore, Gus Yeung | 2000-05-16 |
| 6046930 | Memory array and method for writing data to memory | George McNeil Lattimore, Terry Lee Leasure, Gus Yeung | 2000-04-04 |
| 6025741 | Conditional restore for execution unit | George McNeil Lattimore, Gus Yeung | 2000-02-15 |
| 5970512 | Translation shadow array adder-decoder circuit for selecting consecutive TLB entries | David James Martens | 1999-10-19 |
| 5926487 | High performance registers for pulsed logic | Terry I. Chappell, Max Eduardo De Ycaza, Sang Hoo Dhong, Rudolf A. Haring, Talal K. Jaber +3 more | 1999-07-20 |
| 5896046 | Latch structure for ripple domino logic | Andrew A. Bjorksten, Christopher McCall Durham, Donald George Mikan, Jr. | 1999-04-20 |
| 5896399 | System and method for testing self-timed memory arrays | George McNeil Lattimore, Dieter Wendel, Manoj Kumar, Friedrich-Christian Wernicke | 1999-04-20 |