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Sense amplifier sleep state for leakage savings without bias mismatch |
Russell Schreiber, Eric Busta |
2023-12-26 |
| 11514956 |
Sense amplifier sleep state for leakage savings without bias mismatch |
Russell Schreiber, Eric Busta |
2022-11-29 |
| 10008259 |
Limiting bitline precharge drive fight current using multiple power domains |
— |
2018-06-26 |
| 9953687 |
Pseudo-dynamic circuit for multi-voltage timing interlocks |
John Wuu, Russell Schreiber |
2018-04-24 |
| 8533396 |
Memory elements for performing an allocation operation and related methods |
Michael Kevin Ciraula, Carson D. Henrion |
2013-09-10 |
| 7463537 |
Global bit select circuit interface with dual read and write bit line pairs |
Yuen H. Chan, Antonio R. Pelella, Arthur D. Tuminaro |
2008-12-09 |
| 7336546 |
Global bit select circuit with dual read and write bit line pairs |
Yuen H. Chan, Antonio R. Pelella, Arthur D. Tuminaro |
2008-02-26 |
| 7293209 |
Split L2 latch with glitch free programmable delay |
Yuen H. Chan, Antonio R. Pelella |
2007-11-06 |
| 7272030 |
Global bit line restore timing scheme and circuit |
Yuen H. Chan, Antonio R. Pelella, Uma Srinivasan, Arthur D. Tuminaro, Jatinder K. Wadhwa |
2007-09-18 |
| 7170774 |
Global bit line restore timing scheme and circuit |
Yuen H. Chan, Antonio R. Pelella, Uma Srinivasan, Arthur D. Tuminaro, Jatinder K. Wadhwa |
2007-01-30 |
| 7113433 |
Local bit select with suppression of fast read before write |
Yuen H. Chan, Antonio R. Pelella, Arthur D. Tuminaro |
2006-09-26 |
