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Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same |
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Multi-petascale highly efficient parallel supercomputer |
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System-wide power management control via clock distribution network |
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Power throttling of collections of computing elements |
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Design structure for in-system redundant array repair in integrated circuits |
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Method and apparatus for in-system redundant array repair on integrated circuits |
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Method and apparatus for in-system redundant array repair on integrated circuits |
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Method and apparatus for in-system redundant array repair on integrated circuits |
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Method for incorporating noise considerations in automatic circuit optimization |
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1999-12-07 |
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High performance registers for pulsed logic |
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