Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9599664 | Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures | Luke D. LaCroix, Mark C. Lamorey, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr. +1 more | 2017-03-21 |
| 9172373 | Verifying partial good voltage island structures | Kevin W. Gorman, Michael R. Ouellette, Steven J. Urish | 2015-10-27 |
| 9057760 | Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures | Luke D. LaCroix, Mark C. Lamorey, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr. +1 more | 2015-06-16 |
| 8423847 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Donald L. Wheater | 2013-04-16 |
| 8423844 | Dense register array for enabling scan out observation of both L1 and L2 latches | Pamela S. Gillis, David E. Lackey, Jeffery H. Oppold | 2013-04-16 |
| 8230283 | Method to test hold path faults using functional clocking | Pamela S. Gillis, Vikram Iyengar | 2012-07-24 |
| 8205124 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Donald L. Wheater | 2012-06-19 |
| 8181135 | Hold transition fault model and test generation method | Vikram Iyengar, Pamela S. Gillis, David E. Lackey | 2012-05-15 |
| 7840864 | Functional frequency testing of integrated circuits | Gary D. Grise, Anthony D. Polson, Philip Stevens | 2010-11-23 |
| 7840863 | Functional frequency testing of integrated circuits | Gary D. Grise, Anthony D. Polson, Philip Stevens | 2010-11-23 |
| 7823035 | System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits | David D. Litten | 2010-10-26 |
| 7698611 | Functional frequency testing of integrated circuits | Gary D. Grise, Anthony S. Polson, Philip Stevens | 2010-04-13 |
| 7560964 | Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility | David E. Lackey, Peter Verwegen | 2009-07-14 |
| 7490280 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Donald L. Wheater | 2009-02-10 |
| 7482851 | Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility | David E. Lackey, Peter Verwegen | 2009-01-27 |
| 7456674 | Clock generator having improved deskewer | — | 2008-11-25 |
| 7457187 | Design structure for in-system redundant array repair in integrated circuits | Arthur A. Bright, Paul G. Crumley, Marc Dombrowa, Steven M. Douskey, Rudolf A. Haring +2 more | 2008-11-25 |
| 7428675 | Testing using independently controllable voltage islands | Anne Elizabeth Gattiker, Phil Nigh, Leah Pastel, Jody VanHorn, Paul S. Zuchowski | 2008-09-23 |
| 7405990 | Method and apparatus for in-system redundant array repair on integrated circuits | Arthur A. Bright, Paul G. Crumley, Marc Dombrowa, Steven M. Douskey, Rudolf A. Haring +2 more | 2008-07-29 |
| 7404125 | Compilable memory structure and test methodology for both ASIC and foundry test environments | Steven M. Eustis, James A. Monzel, Michael R. Ouellette | 2008-07-22 |
| 7397709 | Method and apparatus for in-system redundant array repair on integrated circuits | Arthur A. Bright, Paul G. Crumley, Marc Dombrowa, Steven M. Douskey, Rudolf A. Haring +2 more | 2008-07-08 |
| 7310278 | Method and apparatus for in-system redundant array repair on integrated circuits | Arthur A. Bright, Paul G. Crumley, Marc Dombrowa, Steven M. Douskey, Rudolf A. Haring +2 more | 2007-12-18 |
| 7290191 | Functional frequency testing of integrated circuits | Gary D. Grise, Anthony D. Polson, Philip Stevens | 2007-10-30 |
| 7284172 | Access method for embedded JTAG TAP controller instruction registers | Richard J. Grupp, Gary L. Kunselman | 2007-10-16 |
| 7281182 | Method and circuit using boundary scan cells for design library analysis | Pamela S. Gillis, David D. Litten | 2007-10-09 |