Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7243279 | Method for separating shift and scan paths on scan-only, single port LSSD latches | Darren L. Anand, John E. Barth, Jr., Michael R. Ouellette | 2007-07-10 |
| 7089136 | Method for reduced electrical fusing time | Darren L. Anand, John E. Barth, Jr., Michael R. Ouellette | 2006-08-08 |
| 6927614 | High performance state saving circuit | Douglas W. Stout | 2005-08-09 |
| 6856270 | Pipeline array | Henry R. Farmer, David E. Lackey | 2005-02-15 |
| 6768694 | Method of electrically blowing fuses under control of an on-chip tester interface apparatus | Darren L. Anand, Bruce Cowan, L. Farnsworth, Pamela S. Gillis, Peter O. Jakobsen +3 more | 2004-07-27 |
| 6656751 | Self test method and device for dynamic voltage screen functionality improvement | John E. Andersen, Bruce Cowan, Pamela S. Gillis, Michael R. Ouellette | 2003-12-02 |
| 6577156 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Darren L. Anand, John E. Barth, Jr., John A. Fifield, Pamela S. Gillis, Peter O. Jakobsen +4 more | 2003-06-10 |
| 6567943 | D flip-flop structure with flush path for high-speed boundary scan applications | Carl Barnhart, David E. Lackey | 2003-05-20 |
| 6493257 | CMOS state saving latch | Terry C. Coughlin, Jr., Roger P. Gregor, Douglas W. Stout | 2002-12-10 |
| 6304122 | Low power LSSD flip flops and a flushable single clock splitter for flip flops | Roger P. Gregor, Toshiharu Saitoh, Sebastian T. Ventrone | 2001-10-16 |
| 6300809 | Double-edge-triggered flip-flop providing two data transitions per clock cycle | Roger P. Gregor, David J. Hathaway, David E. Lackey | 2001-10-09 |
| 6134682 | Testable bus control logic circuitry and method for using same | — | 2000-10-17 |
| 5925143 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Ravi Kolagotla, Dennis A. Miller, Maria Noack, Chris J. Rebeor +2 more | 1999-07-20 |
| 5920575 | VLSI test circuit apparatus and method | Roger P. Gregor | 1999-07-06 |
| 5825785 | Serial input shift register built-in self test circuit for embedded circuits | Robert L. Barry, John D. Chickanosky, Michael R. Ouellette | 1998-10-20 |
| 5784575 | Output driver that parks output before going tristate | Bijit Thakorbhai Patel, Patrick E. Perry | 1998-07-21 |
| 5719879 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Ravi Kolagotla, Dennis A. Miller, Maria Noack, Chris J. Rebeor +2 more | 1998-02-17 |
| 5625830 | Reduced circuit, high performance, binary select encoder network | Kenneth S. Gray | 1997-04-29 |
| 5311079 | Low power, high performance PLA | Gary S. Ditlow, Dac C. Pham, Kenneth J. Shaw | 1994-05-10 |
| 5272729 | Clock signal latency elimination network | Roland A. Bechade, Frank D. Ferraiolo, Bruce Kaufmann, Ilya I. Novof, Kenneth J. Shaw +1 more | 1993-12-21 |
| 4980889 | Multi-mode testing systems | Wayne J. DeGuise, Charles K. Erdelyi | 1990-12-25 |
| 4868413 | Testable passgate logic circuits | Clarence R. Ogilvie | 1989-09-19 |