| 12340864 |
Interface level-shifter dual-rail memory architecture |
Harold Pilo, Shishir Kumar, Anurag Garg, Peter Lee |
2025-06-24 |
|
| 12014127 |
Transforming a logical netlist into a hierarchical parasitic netlist |
Jeffrey C. Herbert, Matthew Christopher Lanahan |
2024-06-18 |
$101,112,000 |
| 11876516 |
Non-fighting level shifters |
Peter Lee, Kapil Dev Dwivedi |
2024-01-16 |
$208,720,000 |
| 11836433 |
Memory instance reconfiguration using super leaf cells |
Jeffrey C. Herbert, Matthew Christopher Lanahan |
2023-12-05 |
$70,386,000 |
| 11074496 |
Providing transposable access to a synapse array using a recursive array layout |
John V. Arthur, Paul A. Merolla, Dharmendra S. Modha |
2021-07-27 |
$4,187,000 |
| 11017873 |
Memory bypass function for a memory |
Kevin W. Gorman, Harold Pilo |
2021-05-25 |
$124,663,000 |
| 10957391 |
Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits |
Dean L. Lewis |
2021-03-23 |
$2,115,000 |
| 10740282 |
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2020-08-11 |
$2,122,000 |
| 10706916 |
Method and apparatus for integrated level-shifter and memory clock |
Harold Pilo |
2020-07-07 |
$43,617,000 |
| 10650906 |
Memory bypass function for a memory |
Kevin W. Gorman, Harold Pilo |
2020-05-12 |
$32,020,000 |
| 10431307 |
Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits |
Dean L. Lewis |
2019-10-01 |
$3,685,000 |
| 10176063 |
Faulty core recovery mechanisms for a three-dimensional network on a processor array |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more |
2019-01-08 |
$2,287,000 |
| 9965718 |
Providing transposable access to a synapse array using a recursive array layout |
John V. Arthur, Paul A. Merolla, Dharmendra S. Modha |
2018-05-08 |
$5,367,000 |
| 9940302 |
Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2018-04-10 |
$2,135,000 |
| 9792251 |
Array of processor core circuits with reversible tiers |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2017-10-17 |
$4,096,000 |
| 9741722 |
Dummy gate structure for electrical isolation of a fin DRAM |
Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan +4 more |
2017-08-22 |
$2,056,000 |
| 9735162 |
Dynamic random access memory cell with self-aligned strap |
Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim +1 more |
2017-08-15 |
$1,588,000 |
| 9620179 |
Sense amplifier and methods thereof for single ended line sensing |
— |
2017-04-11 |
|
| 9613700 |
TCAM field enable logic |
Harold Pilo, Gerald P. Pomichter, Jr., Michael Lee |
2017-04-04 |
|
| 9588937 |
Array of processor core circuits with reversible tiers |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2017-03-07 |
$2,625,000 |
| 9570363 |
Vertically integrated memory cell |
Babar A. Khan |
2017-02-14 |
$1,939,000 |
| 9564184 |
Sense amplifier for single-ended sensing |
— |
2017-02-07 |
|
| 9564183 |
Sense amplifier having a timing circuit for a presearch and a main search |
— |
2017-02-07 |
|
| 9564445 |
Dummy gate structure for electrical isolation of a fin DRAM |
Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan +4 more |
2017-02-07 |
$2,910,000 |
| 9564443 |
Dynamic random access memory cell with self-aligned strap |
Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim +1 more |
2017-02-07 |
$2,910,000 |
