Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353717 | Localized and relocatable software placement and NoC-based access to memory controllers | Aman Gupta, Krishnan Srinivasan, Sagheer Ahmad, Ahmad R. Ansari | 2025-07-08 |
| 12354656 | Reducing memory device bitline leakage | Vinay Kumar | 2025-07-08 |
| 12340864 | Interface level-shifter dual-rail memory architecture | Harold Pilo, Anurag Garg, Peter Lee, John E. Barth, Jr. | 2025-06-24 |
| 12316326 | Delay circuit | Vinay Kumar | 2025-05-27 |
| 12272424 | Reducing spurious write operations in a memory device | Vinay Kumar | 2025-04-08 |
| 12112818 | Scan chain compression for testing memory of a system on a chip | Harold Pilo | 2024-10-08 |
| 12094513 | Power supply tracking circuitry for embedded memories | Harold Pilo, Anurag Garg | 2024-09-17 |
| 12019908 | Dynamically allocated buffer pooling | Krishnan Srinivasan, Sagheer Ahmad, Abbas Morshed, Aman Gupta | 2024-06-25 |
| 11889675 | Dual port memory cell with improved access resistance | Tushar Sharma, Tanmoy Roy | 2024-01-30 |
| 11742045 | Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory | Rohit Bhasin, Tanmoy Roy, Deepak Kumar Bihani | 2023-08-29 |
| 11532633 | Dual port memory cell with improved access resistance | Tushar Sharma, Tanmoy Roy | 2022-12-20 |
| 11521697 | Circuit and method for at speed detection of a word line fault condition in a memory circuit | Abhishek Pathak | 2022-12-06 |
| 11393532 | Circuit and method for at speed detection of a word line fault condition in a memory circuit | Tanmoy Roy, Tanuj KUMAR | 2022-07-19 |
| 11195576 | Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier | Bhupender Singh | 2021-12-07 |
| 11152376 | Dual port memory cell with improved access resistance | Tushar Sharma, Tanmoy Roy | 2021-10-19 |
| 11025252 | Circuit for detection of single bit upsets in generation of internal clock for memory | Tanuj KUMAR, Deepak Kumar Bihani | 2021-06-01 |
| 10998077 | Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory | Rohit Bhasin, Tanmoy Roy, Deepak Kumar Bihani | 2021-05-04 |
| 10706915 | Method and circuit for adaptive read-write operation in self-timed memory | Abhishek Pathak, Tanmoy Roy | 2020-07-07 |
| 10311944 | SRAM read multiplexer including replica transistors | Dhori Kedar Janardan, Abhishek Pathak | 2019-06-04 |
| 10283191 | Method and circuit for adaptive read-write operation in self-timed memory | Abhishek Pathak, Tanmoy Roy | 2019-05-07 |
| 10191902 | Method and unit for building semantic rule for a semantic data | — | 2019-01-29 |
| 10073838 | Method and system for enabling verifiable semantic rule building for semantic data | — | 2018-09-11 |
| 10037794 | SRAM read multiplexer including replica transistors | Dhori Kedar Janardan, Abhishek Pathak | 2018-07-31 |
| 9910880 | System and method for managing enterprise user group | Jayakumar Panicker | 2018-03-06 |
| 9898527 | Methods for retrieving information and devices thereof | — | 2018-02-20 |