Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Harsh Rawat, Kedar Janardan Dhori, Promod Kumar +2 more | 2025-07-08 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori, Manuj AYODHYAWASI +2 more | 2024-12-17 |
| 11393532 | Circuit and method for at speed detection of a word line fault condition in a memory circuit | Tanmoy Roy, Shishir Kumar | 2022-07-19 |
| 11025252 | Circuit for detection of single bit upsets in generation of internal clock for memory | Shishir Kumar, Deepak Kumar Bihani | 2021-06-01 |