Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI | 2025-09-02 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Nitin Chawla, Kedar Janardan Dhori, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Kedar Janardan Dhori +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI, Harsh Rawat | 2025-07-08 |
| 12328858 | Silicon-on-insulator semiconductor device with a static random access memory circuit | Olivier Weber, Kedar Janardan Dhori, Shafquat Jahan Ahmed, Christophe Lecocq, Pascal Urard | 2025-06-10 |
| 12292780 | Computing system power management device, system and method | Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch | 2025-05-06 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Harsh Rawat, Nitin Chawla, Manuj AYODHYAWASI | 2025-02-25 |
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more | 2024-12-17 |
| 12159689 | SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications | Praveen Kumar Verma, Harsh Rawat | 2024-12-03 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI | 2024-09-10 |
| 12046324 | Modular memory architecture with gated sub-array operation dependent on stored data content | Harsh Rawat, Praveen Kumar Verma, Christophe Lecocq | 2024-07-23 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI | 2024-05-14 |
| 11726543 | Computing system power management device, system and method | Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch | 2023-08-15 |
| 8269545 | Fail safe adaptive voltage/frequency system | Nitin Chawla, Chittoor Parthasarathy, Kallol Chatterjee | 2012-09-18 |
| 8218377 | Fail-safe high speed level shifter for wide supply voltage range | Amit Tandon, Abhishek Lal | 2012-07-10 |
| 8154335 | Fail safe adaptive voltage/frequency system | Nitin Chawla, Chittoor Parthasarathy, Kallol Chatterjee | 2012-04-10 |
| 7750689 | High voltage switch with reduced voltage stress at output stage | Vikas Rana, Abhishek Lal | 2010-07-06 |
| 7050343 | Built-in testing methodology in flash memory | Francesco Tomaiuolo, Pierpaolo Nicosia, Luca De Ambroggi, Francesco Pipitone | 2006-05-23 |
| 6638818 | Method of fabricating a dynamic random access memory with increased capacitance | Darius Crenshaw | 2003-10-28 |
| 6624679 | Stabilized delay circuit | Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca De Ambroggi | 2003-09-23 |
| 6625706 | ATD generation in a synchronous memory | Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca De Ambroggi | 2003-09-23 |
| 6587913 | Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode | Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca De Ambroggi, Luigi Pascucci | 2003-07-01 |
| 6487140 | Circuit for managing the transfer of data streams from a plurality of sources within a system | Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca De Ambroggi | 2002-11-26 |