| 12482518 |
Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current |
Kedar Janardan Dhori, Nitin Chawla, Harsh Rawat, Manuj AYODHYAWASI |
2025-11-25 |
|
| 12469545 |
Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Kedar Janardan Dhori, Nitin Chawla, Harsh Rawat, Manuj AYODHYAWASI |
2025-11-11 |
|
| 12437825 |
At-speed transition fault testing for a multi-port and multi-clock memory |
Tanuj KUMAR, Hitesh Chawla, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more |
2025-10-07 |
|
| 12406705 |
In-memory computation circuit using static random access memory (SRAM) array segmentation |
Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI |
2025-09-02 |
|
| 12361982 |
Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode |
Harsh Rawat, Nitin Chawla, Kedar Janardan Dhori, Manuj AYODHYAWASI |
2025-07-15 |
|
| 12354644 |
Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI, Harsh Rawat |
2025-07-08 |
|
| 12353341 |
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection |
Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Kedar Janardan Dhori +2 more |
2025-07-08 |
|
| 12328858 |
Silicon-on-insulator semiconductor device with a static random access memory circuit |
Olivier Weber, Kedar Janardan Dhori, Shafquat Jahan Ahmed, Christophe Lecocq, Pascal Urard |
2025-06-10 |
|
| 12292780 |
Computing system power management device, system and method |
Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch |
2025-05-06 |
|
| 12237007 |
Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Kedar Janardan Dhori, Harsh Rawat, Nitin Chawla, Manuj AYODHYAWASI |
2025-02-25 |
|
| 12183424 |
Bit-cell architecture based in-memory compute |
Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI |
2024-12-31 |
$22,639,000 |
| 12176025 |
Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI |
2024-12-24 |
$22,753,000 |
| 12170120 |
Built-in self test circuit for segmented static random access memory (SRAM) array input/output |
Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more |
2024-12-17 |
$45,720,000 |
| 12159689 |
SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications |
Praveen Kumar Verma, Harsh Rawat |
2024-12-03 |
$22,998,000 |
| 12087356 |
Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI |
2024-09-10 |
$12,064,000 |
| 12046324 |
Modular memory architecture with gated sub-array operation dependent on stored data content |
Harsh Rawat, Praveen Kumar Verma, Christophe Lecocq |
2024-07-23 |
|
| 11984151 |
Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
Harsh Rawat, Kedar Janardan Dhori, Nitin Chawla, Manuj AYODHYAWASI |
2024-05-14 |
$23,579,000 |
| 11726543 |
Computing system power management device, system and method |
Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch |
2023-08-15 |
$30,975,000 |
| 8269545 |
Fail safe adaptive voltage/frequency system |
Nitin Chawla, Chittoor Parthasarathy, Kallol Chatterjee |
2012-09-18 |
$5,959,000 |
| 8218377 |
Fail-safe high speed level shifter for wide supply voltage range |
Amit Tandon, Abhishek Lal |
2012-07-10 |
$3,654,000 |
| 8154335 |
Fail safe adaptive voltage/frequency system |
Nitin Chawla, Chittoor Parthasarathy, Kallol Chatterjee |
2012-04-10 |
$5,538,000 |
| 7750689 |
High voltage switch with reduced voltage stress at output stage |
Vikas Rana, Abhishek Lal |
2010-07-06 |
$4,056,000 |
| 7050343 |
Built-in testing methodology in flash memory |
Francesco Tomaiuolo, Pierpaolo Nicosia, Luca De Ambroggi, Francesco Pipitone |
2006-05-23 |
$4,072,000 |
| 6638818 |
Method of fabricating a dynamic random access memory with increased capacitance |
Darius Crenshaw |
2003-10-28 |
$33,381,000 |
| 6625706 |
ATD generation in a synchronous memory |
Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca De Ambroggi |
2003-09-23 |
$14,097,000 |