Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

US Patent 12469545 · Granted Nov 11, 2025

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
In-memory computation circuit using static random access memory (SRAM) array seg2025
In-memory computation circuit using static random access memory (SRAM) array seg2025