Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-09-02 |
| 12400707 | Device and method for reading data from memory cells | — | 2025-08-26 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Nitin Chawla, Promod Kumar, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Promod Kumar +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Nitin Chawla, Promod Kumar, Manuj AYODHYAWASI, Harsh Rawat | 2025-07-08 |
| 12328858 | Silicon-on-insulator semiconductor device with a static random access memory circuit | Olivier Weber, Promod Kumar, Shafquat Jahan Ahmed, Christophe Lecocq, Pascal Urard | 2025-06-10 |
| 12292780 | Computing system power management device, system and method | Nitin Chawla, Anuj Grover, Giuseppe Desoli, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-02-25 |
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Manuj AYODHYAWASI +2 more | 2024-12-17 |
| 12165698 | Circuitry for adjusting retention voltage of a static random access memory (SRAM) | — | 2024-12-10 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-09-10 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-05-14 |
| 11758707 | SRAM cell layout including arrangement of multiple active regions and multiple gate regions | Shafquat Jahan Ahmed | 2023-09-12 |
| 11726543 | Computing system power management device, system and method | Nitin Chawla, Anuj Grover, Giuseppe Desoli, Thomas Boesch, Promod Kumar | 2023-08-15 |
| 10224097 | Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation | Ashish Kumar, Vinay Kumar | 2019-03-05 |
| 9940997 | Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation | Ashish Kumar, Vinay Kumar | 2018-04-10 |
| 9865333 | Temperature compensated read assist circuit for a static random access memory (SRAM) | Ashish Kumar, Hitesh Chawla, Praveen Kumar Verma | 2018-01-09 |
| 9685209 | Circuit for generating a sense amplifier enable signal with variable timing | Vinay Kumar, Ashish Kumar | 2017-06-20 |
| 9208040 | Repair control logic for safe memories having redundant elements | Harsh Rawat, Vinay Kumar, PraveenKumar Verma | 2015-12-08 |
| 8154936 | Single-ended bit line based storage system | — | 2012-04-10 |