Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-09-02 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Nitin Chawla, Promod Kumar, Kedar Janardan Dhori, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Kedar Janardan Dhori, Promod Kumar +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Nitin Chawla, Promod Kumar, Manuj AYODHYAWASI | 2025-07-08 |
| 12340099 | Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion | Praveen Kumar Verma | 2025-06-24 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-02-25 |
| 12183424 | Bit-cell architecture based in-memory compute | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Kedar Janardan Dhori, Manuj AYODHYAWASI +2 more | 2024-12-17 |
| 12159689 | SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications | Praveen Kumar Verma, Promod Kumar | 2024-12-03 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-09-10 |
| 12068026 | Low power and fast memory reset | Praveen Kumar Verma | 2024-08-20 |
| 12046324 | Modular memory architecture with gated sub-array operation dependent on stored data content | Praveen Kumar Verma, Promod Kumar, Christophe Lecocq | 2024-07-23 |
| 12040013 | Static random access memory supporting a single clock cycle read-modify-write operation | Praveen Kumar Verma | 2024-07-16 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-05-14 |
| 10249363 | Configurable pseudo dual port architecture for use with single port SRAM | Abhishek Pathak | 2019-04-02 |
| 10032506 | Configurable pseudo dual port architecture for use with single port SRAM | Abhishek Pathak | 2018-07-24 |
| 9786364 | Low voltage selftime tracking circuitry for write assist based memory operation | Abhishek Pathak | 2017-10-10 |
| 9524242 | Cache memory system with simultaneous read-write in single cycle | Piyush Jain, Gangaikondan Subramani Visweswaran | 2016-12-20 |
| 9311990 | Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods | Piyush Jain | 2016-04-12 |
| 9208040 | Repair control logic for safe memories having redundant elements | Kedar Janardan Dhori, Vinay Kumar, PraveenKumar Verma | 2015-12-08 |
| 8458545 | Method and apparatus for testing of a memory with redundancy elements | Tanmoy Roy, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria | 2013-06-04 |
| 8144537 | Balanced sense amplifier for single ended bitline memory architecture | Anand Mishra | 2012-03-27 |