Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla | 2025-09-02 |
| 12386506 | Tagged memory operated at lower VMIN in error tolerant system | Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh | 2025-08-12 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Nitin Chawla, Promod Kumar, Kedar Janardan Dhori | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Kedar Janardan Dhori +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Nitin Chawla, Promod Kumar, Harsh Rawat | 2025-07-08 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Harsh Rawat, Promod Kumar, Nitin Chawla | 2025-02-25 |
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more | 2024-12-17 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla | 2024-09-10 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla | 2024-05-14 |
| 11900240 | Variable clock adaptation in neural network processors | Nitin Chawla, Giuseppe Desoli, Thomas Boesch, Surinder Singh | 2024-02-13 |
| 11836346 | Tagged memory operated at lower vmin in error tolerant system | Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh | 2023-12-05 |
| 11360667 | Tagged memory operated at lower vmin in error tolerant system | Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh | 2022-06-14 |
| 7750673 | Interconnect structure and method in programmable devices | Kailash Digari | 2010-07-06 |