Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148473 | Non-volatile memory cell with single poly, floating gate extending over two wells | Roberto Bregoli | 2024-11-19 |
| 12094542 | Device and method to generate bias voltages in non-volatile memory | Neha DALAL | 2024-09-17 |
| 12087368 | Circuit and method for on-chip leakage detection and compensation for memories | Arpit VIJAYVERGIA | 2024-09-10 |
| 12033715 | Memory circuit arrangement for accurate and secure read | Arpit VIJAYVERGIA | 2024-07-09 |
| 11935607 | Circuit and method to detect word-line leakage and process defects in non-volatile memory array | Vivek Tyagi | 2024-03-19 |
| 11908528 | Selectively configurable charge pump | Arpit VIJAYVERGIA | 2024-02-20 |
| 11881280 | Circuit and method for constant slew rate in high voltage charge pumps | Shivam Kalla | 2024-01-23 |
| 11863066 | Positive and negative charge pump control | Marco Pasotti, Fabio De Santis | 2024-01-02 |
| 11798603 | Circuit for generating and trimming phases for memory cell read operations | Vivek Tyagi, Chantal Auricchio, Laura Capecchi | 2023-10-24 |
| 11764673 | NMOS-based negative charge pump circuit | — | 2023-09-19 |
| 11665915 | Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof | Fabio De Santis | 2023-05-30 |
| 11615820 | Regulator of a sense amplifier | Laura Capecchi, Marcella Carissimi, Marco Pasotti, Vivek Tyagi | 2023-03-28 |
| 11615823 | Circuit for generating and trimming phases for memory cell read operations | Vivek Tyagi, Chantal Auricchio, Laura Capecchi | 2023-03-28 |
| 11611275 | Positive and negative charge pump control | Marco Pasotti, Fabio De Santis | 2023-03-21 |
| 11563373 | Circuit and method for controlled discharge of a high (positive or negative) voltage charge pump | Neha DALAL | 2023-01-24 |
| 11551731 | Memory circuit arrangement for accurate and secure read | Arpit VIJAYVERGIA | 2023-01-10 |
| 11522446 | Low input supply and low output impedance charge pump circuit configured for positive and negative voltage generation | — | 2022-12-06 |
| 11475960 | Non-volatile memory device with a program driver circuit including a voltage limiter | Fabio Enrico Carlo Disegni, Laura Capecchi, Marcella Carissimi, Cesare Torti | 2022-10-18 |
| 11424676 | Positive and negative charge pump control | Marco Pasotti, Fabio De Santis | 2022-08-23 |
| 11356018 | Charge pump circuit configured for positive and negative voltage generation | — | 2022-06-07 |
| 11342031 | Circuit and method for process and temperature compensated read voltage for non-volatile memory | Marco Pasotti, Dario Livornesi, Roberto Bregoli, Abhishek Mittal | 2022-05-24 |
| 11258358 | Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory | Shivam Kalla | 2022-02-22 |
| 11205462 | Circuit for generating and trimming phases for memory cell read operations | Vivek Tyagi, Chantal Auricchio, Laura Capecchi | 2021-12-21 |
| 11183924 | Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation | — | 2021-11-23 |
| 11070128 | Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory | Shivam Kalla | 2021-07-20 |