Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12266415 | Reliable electronic fuse based storage using error correction coding | Paul J. Grzymkowski, John R. Goss | 2025-04-01 |
| 11017873 | Memory bypass function for a memory | John E. Barth, Jr., Harold Pilo | 2021-05-25 |
| 10650906 | Memory bypass function for a memory | John E. Barth, Jr., Harold Pilo | 2020-05-12 |
| 10622090 | Arbitration for memory diagnostics | Aravindan J. Busi, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette | 2020-04-14 |
| 10153055 | Arbitration for memory diagnostics | Aravindan J. Busi, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette | 2018-12-11 |
| 9946620 | Memory built-in self test system | Thomas Chadwick, Nancy H. Pratt | 2018-04-17 |
| 9865361 | Diagnostics for a memory device | Thomas Chadwick, Nancy H. Pratt | 2018-01-09 |
| 9799413 | Multi-domain fuse management | Thomas Chadwick, Nancy H. Pratt | 2017-10-24 |
| 9773570 | Built-in-self-test (BIST) test time reduction | Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette | 2017-09-26 |
| 9734920 | Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories | Michael R. Ouellette, Patrick E. Perry | 2017-08-15 |
| 9514844 | Fast auto shift of failing memory diagnostics data using pattern detection | Aravindan J. Busi, Kiran K. Narayan, Michael R. Ouellette | 2016-12-06 |
| 9460811 | Read only memory (ROM) with redundancy | George M. Braceras, Albert M. Chu, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2016-10-04 |
| 9224503 | Memory test with in-line error correction code logic | Michael R. Ouellette, Patrick E. Perry | 2015-12-29 |
| 9172373 | Verifying partial good voltage island structures | Steven F. Oakland, Michael R. Ouellette, Steven J. Urish | 2015-10-27 |
| 8935586 | Staggered start of BIST controllers and BIST engines | Valarie H. Chickanosky, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer | 2015-01-13 |
| 8917566 | Bypass structure for a memory device and method to reduce unknown test values | Aaron Cummings, Michael T. Fragano, Kelly A. Ockunzzi, Michael R. Ouellette | 2014-12-23 |
| 8914688 | System and method of reducing test time via address aware BIST circuitry | George M. Belansek, Kiran K. Narayan, Krishnendu Mondal, Michael R. Ouellette | 2014-12-16 |
| 8839054 | Read only memory (ROM) with redundancy | George M. Braceras, Albert M. Chu, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2014-09-16 |
| 8719648 | Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture | Michael R. Ouellette, Michael A. Ziegerhofer | 2014-05-06 |
| 8612813 | Circuit and method for efficient memory repair | Valerie H. Chickanosky, Suzanne Granato, Michael R. Ouellette | 2013-12-17 |
| 8570820 | Selectable repair pass masking | John R. Goss, Michael R. Ouellette, Troy J. Perry, Michael A. Ziegerhofer | 2013-10-29 |
| 8484543 | Fusebay controller structure, system, and method | Darren L. Anand, Michael R. Ouellette, Michael A. Ziegerhofer | 2013-07-09 |
| 8467260 | Structure and method for storing multiple repair pass data into a fusebay | Michael R. Ouellette, Michael A. Ziegerhofer | 2013-06-18 |
| 8381052 | Circuit and method for efficient memory repair | Valerie H. Chickanosky, Suzanne Granato, Michael R. Ouellette | 2013-02-19 |
| 8239715 | Method and apparatus for a robust embedded interface | Steven M. Eustis, David E. Lackey, Michael R. Ouellette | 2012-08-07 |