Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11295829 | Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register | Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Kiran K. Narayan, Michael R. Ouellette +1 more | 2022-04-05 |
| 10971243 | Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register | Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Kiran K. Narayan, Michael R. Ouellette +1 more | 2021-04-06 |
| 10692584 | Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register | Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Kiran K. Narayan, Michael R. Ouellette +1 more | 2020-06-23 |
| 10658062 | Simultaneous scan chain initialization with disparate latches | Mitesh Agrawal, Benedikt Geukes | 2020-05-19 |
| 10586606 | Simultaneous scan chain initialization with disparate latches | Mitesh Agrawal, Benedikt Geukes | 2020-03-10 |
| 10553302 | Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register | Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Kiran K. Narayan, Michael R. Ouellette +1 more | 2020-02-04 |
| 10199121 | Simultaneous scan chain initialization with disparate latches | Mitesh Agrawal, Benedikt Geukes | 2019-02-05 |
| 10096377 | Simultaneous scan chain initialization with disparate latches | Mitesh Agrawal, Benedikt Geukes | 2018-10-09 |
| 10026498 | Simultaneous scan chain initialization with disparate latches | Mitesh Agrawal, Benedikt Geukes | 2018-07-17 |
| 10014074 | Failure analysis and repair register sharing for memory BIST | Deepak I. Hanagandi, Michael R. Ouellette, Valerie H. Chickanosky | 2018-07-03 |
| 9881694 | Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register | Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Kiran K. Narayan, Michael R. Ouellette +1 more | 2018-01-30 |
| 9859019 | Programmable counter to control memory built in self-test | Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer | 2018-01-02 |
| 9773570 | Built-in-self-test (BIST) test time reduction | Kevin W. Gorman, Deepak I. Hanagandi, Michael R. Ouellette | 2017-09-26 |
| 9761329 | Built-in self-test (BIST) circuit and associated BIST method for embedded memories | Aravindan J. Busi, Deepak I. Hanagandi, Michael R. Ouellette | 2017-09-12 |
| 9715942 | Built-in self-test (BIST) circuit and associated BIST method for embedded memories | Aravindan J. Busi, Deepak I. Hanagandi, Michael R. Ouellette | 2017-07-25 |
| 8918690 | Decreasing power supply demand during BIST initializations | Deepak I. Hanagandi, Michael R. Ouellette, Michael A. Ziegerhofer | 2014-12-23 |
| 8914688 | System and method of reducing test time via address aware BIST circuitry | George M. Belansek, Kevin W. Gorman, Kiran K. Narayan, Michael R. Ouellette | 2014-12-16 |
| 8872322 | Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks | Kevin W. Gorman, Derek H. Leu, Saravanan Sethuraman | 2014-10-28 |
| 8853847 | Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks | Kevin W. Gorman, Saravanan Sethuraman | 2014-10-07 |
| 6928377 | Self-test architecture to implement data column redundancy in a RAM | Steven M. Eustis, Michael R. Ouellette, Jeremy Rowland | 2005-08-09 |
| 6922649 | Multiple on-chip test runs and repairs for memories | Michael R. Ouellette | 2005-07-26 |
| 6768694 | Method of electrically blowing fuses under control of an on-chip tester interface apparatus | Darren L. Anand, Bruce Cowan, L. Farnsworth, Pamela S. Gillis, Peter O. Jakobsen +3 more | 2004-07-27 |