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High efficiency on-chip 3D transformer structure |
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High efficiency on-chip 3D transformer structure |
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High efficiency on-chip 3D transformer structure |
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High efficiency on-chip 3D transformer structure |
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Segmented guard ring structures with electrically insulated gap structures and design structures thereof |
Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg +1 more |
2015-03-24 |
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Folded conical inductor |
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Chip seal ring having a serpentine geometry |
— |
2008-12-16 |
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Complementary two transistor ROM cell |
Peter F. Croce, Steven M. Eustis, Yabin Wang |
2005-07-26 |
| 6778419 |
Complementary two transistor ROM cell |
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2004-08-17 |
| 6675273 |
Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested |
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2004-01-06 |
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Serial input shift register built-in self test circuit for embedded circuits |
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1998-10-20 |
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Read only memory having localized reference bit lines |
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1997-02-11 |
| 5040145 |
Memory cell with active write load |
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1991-08-13 |
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Directory memory system having simultaneous write, compare and bypass capabilites |
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1987-05-05 |
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Dual mode logic circuit for a memory array |
— |
1986-08-26 |
