Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11011295 | High efficiency on-chip 3D transformer structure | Robert A. Groves, Venkata Nr. Vanukuru | 2021-05-18 |
| 10049806 | High efficiency on-chip 3D transformer structure | Robert A. Groves, Venkata Nr. Vanukuru | 2018-08-14 |
| 9831026 | High efficiency on-chip 3D transformer structure | Venkata Nr. Vanukuru | 2017-11-28 |
| 9779869 | High efficiency on-chip 3D transformer structure | Robert A. Groves, Venkata Nr. Vanukuru | 2017-10-03 |
| 9431164 | High efficiency on-chip 3D transformer structure | Venkata Nr. Vanukuru | 2016-08-30 |
| 9318620 | Folded conical inductor | Robert A. Groves, Venkata N.R. Vanukuru | 2016-04-19 |
| 9251948 | High efficiency on-chip 3D transformer structure | Venkata Nr. Vanukuru | 2016-02-02 |
| 9171663 | High efficiency on-chip 3D transformer structure | Robert A. Groves, Venkata Nr. Vanukuru | 2015-10-27 |
| 8987067 | Segmented guard ring structures with electrically insulated gap structures and design structures thereof | Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg +1 more | 2015-03-24 |
| 8836460 | Folded conical inductor | Robert A. Groves, Venkata N.R. Vanukuru | 2014-09-16 |
| 7466284 | Chip seal ring having a serpentine geometry | — | 2008-12-16 |
| 6922349 | Complementary two transistor ROM cell | Peter F. Croce, Steven M. Eustis, Yabin Wang | 2005-07-26 |
| 6778419 | Complementary two transistor ROM cell | Peter F. Croce, Steven M. Eustis, Yabin Wang | 2004-08-17 |
| 6675273 | Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested | Steven M. Eustis, Peter F. Croce | 2004-01-06 |
| 5825785 | Serial input shift register built-in self test circuit for embedded circuits | John D. Chickanosky, Steven F. Oakland, Michael R. Ouellette | 1998-10-20 |
| 5602788 | Read only memory having localized reference bit lines | John D. Chickanosky | 1997-02-11 |
| 5040145 | Memory cell with active write load | John E. Andersen, James N. Bisnett, Eric G. Fung | 1991-08-13 |
| 4663742 | Directory memory system having simultaneous write, compare and bypass capabilites | John E. Andersen, Kenneth H. Christie, Dennis J. Shea | 1987-05-05 |
| 4608667 | Dual mode logic circuit for a memory array | — | 1986-08-26 |