Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978452 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2021-04-13 |
| 10170476 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2019-01-01 |
| 9842838 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2017-12-12 |
| 9397010 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2016-07-19 |
| 9275997 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2016-03-01 |
| 8987067 | Segmented guard ring structures with electrically insulated gap structures and design structures thereof | Robert L. Barry, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg +1 more | 2015-03-24 |
| 8853789 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2014-10-07 |
| 8420518 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2013-04-16 |
| 8212332 | Bias-controlled deep trench substrate noise isolation integrated circuit device structures | David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh +1 more | 2012-07-03 |
| 8021941 | Bias-controlled deep trench substrate noise isolation integrated circuit device structures | David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh +1 more | 2011-09-20 |
| 8017471 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | David S. Collins, Steven H. Voldman | 2011-09-13 |
| 7855420 | Structure for a latchup robust array I/O using through wafer via | David S. Collins, Steven H. Voldman | 2010-12-21 |
| 7741681 | Latchup robust array I/O using through wafer via | David S. Collins, Steven H. Voldman | 2010-06-22 |
| 7696541 | Structure for a latchup robust gate array using through wafer via | David S. Collins, Steven H. Voldman | 2010-04-13 |
| 7549135 | Design methodology of guard ring design resistance optimization for latchup prevention | David S. Collins, Steven H. Voldman | 2009-06-16 |
| 7498622 | Latchup robust gate array using through wafer via | David S. Collins, Steven H. Voldman | 2009-03-03 |
| 6391661 | Semiconductor and method of fabricating | Daniel S. Brooks, John Cronin, Richard Wistrom | 2002-05-21 |
| 6229155 | Semiconductor and method of fabricating | Daniel S. Brooks, John Cronin, Richard Wistrom | 2001-05-08 |