| 10978452 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2021-04-13 |
$3,936,000 |
| 10170476 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2019-01-01 |
|
| 9842838 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2017-12-12 |
$7,756,000 |
| 9397010 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2016-07-19 |
$4,161,000 |
| 9275997 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2016-03-01 |
$3,006,000 |
| 8853789 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2014-10-07 |
$3,450,000 |
| 8674423 |
Semiconductor structure having vias and high density capacitors |
Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel |
2014-03-18 |
$3,993,000 |
| 8420518 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2013-04-16 |
$3,567,000 |
| 8288244 |
Lateral passive device having dual annular electrodes |
Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel, David C. Sheridan |
2012-10-16 |
$3,795,000 |
| 8288821 |
SOI (silicon on insulator) substrate improvements |
Alan B. Botula, Alvin J. Joseph, Howard S. Landis, James A. Slinkman |
2012-10-16 |
$3,795,000 |
| 8234606 |
Metal wiring structure for integration with through substrate vias |
Alvin J. Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson |
2012-07-31 |
$5,473,000 |
| 8169007 |
Asymmetric junction field effect transistor |
Frederick G. Anderson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak |
2012-05-01 |
$7,417,000 |
| 8138607 |
Metal fill structures for reducing parasitic capacitance |
Howard S. Landis, Anthony K. Stamper, Janet M. Wilson |
2012-03-20 |
$2,170,000 |
| 8125013 |
Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors |
Kai D. Feng, Zhong-Xiang Ile, Peter J. Lindgren, Robert M. Rassel |
2012-02-28 |
$6,579,000 |
| 8101494 |
Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors |
Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel |
2012-01-24 |
$7,514,000 |
| 8089126 |
Method and structures for improving substrate loss and linearity in SOI substrates |
Alan B. Botula, Alvin J. Joseph, Howard S. Landis, James A. Slinkman, Anthony K. Stamper |
2012-01-03 |
$8,800,000 |
| 8017471 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
Phillip F. Chapman, Steven H. Voldman |
2011-09-13 |
$4,804,000 |
| 8008748 |
Deep trench varactors |
Robert M. Rassel, Eric Thompson |
2011-08-30 |
$4,619,000 |
| 7968975 |
Metal wiring structure for integration with through substrate vias |
Alvin J. Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson |
2011-06-28 |
$4,369,000 |
| 7943445 |
Asymmetric junction field effect transistor |
Frederick G. Anderson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak |
2011-05-17 |
$5,524,000 |
| 7868423 |
Optimized device isolation |
John Benoit, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel +2 more |
2011-01-11 |
$2,856,000 |
| 7855420 |
Structure for a latchup robust array I/O using through wafer via |
Phillip F. Chapman, Steven H. Voldman |
2010-12-21 |
$6,138,000 |
| 7821097 |
Lateral passive device having dual annular electrodes |
Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel, David C. Sheridan |
2010-10-26 |
$4,266,000 |
| 7741681 |
Latchup robust array I/O using through wafer via |
Phillip F. Chapman, Steven H. Voldman |
2010-06-22 |
$6,664,000 |
| 7739636 |
Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise |
Mete Erturk, Edward J. Gordon, Robert A. Groves, Robert M. Rassel |
2010-06-15 |
$4,416,000 |
