Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

US Patent 9842838 · Granted Dec 12, 2017

Estimated economic value: $7,756,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Structure and method of latchup robustness with placement of through wafer via w2021
Structure and method of latchup robustness with placement of through wafer via w2021
Structure and method of latchup robustness with placement of through wafer via w2021
Method for forming FinFET device structure2020
Structure and method of latchup robustness with placement of through wafer via w2019
Structure and method of latchup robustness with placement of through wafer via w2019
Structure and method of latchup robustness with placement of through wafer via w2019
FinFET device structure and method for forming same2018
Structure and method of latchup robustness with placement of through wafer via w2016
Structure and method of latchup robustness with placement of through wafer via w2016
Structure and method of latchup robustness with placement of through wafer via w2016
Structure and method of latchup robustness with placement of through wafer via w2016