Issued Patents All Time
Showing 25 most recent of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978452 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2021-04-13 |
| 10615260 | Method for forming FinFET device structure | — | 2020-04-07 |
| 10170476 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2019-01-01 |
| 10038058 | FinFET device structure and method for forming same | — | 2018-07-31 |
| 9842838 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2017-12-12 |
| 9397010 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2016-07-19 |
| 9275997 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2016-03-01 |
| 9087925 | Si and SiGeC on a buried oxide layer on a substrate | Xuefeng Liu, Robert M. Rassel | 2015-07-21 |
| 8994026 | Structure, structure and method of latch-up immunity for high and low voltage integrated circuits | — | 2015-03-31 |
| 8963158 | Structure, structure and method of latch-up immunity for high and low voltage integrated circuits | — | 2015-02-24 |
| 8962480 | ESD network circuit with a through wafer via structure and a method of manufacture | — | 2015-02-24 |
| 8946013 | Lateral diffusion field effect transistor with drain region self-aligned to gate electrode | Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Michael J. Zierak | 2015-02-03 |
| 8859337 | Thermal matching in semiconductor devices using heat distribution structures | Stephen Joseph Gaul, Jean-Michel Tschann | 2014-10-14 |
| 8853789 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2014-10-07 |
| 8847317 | Isolated epitaxial modulation device | Yu Li | 2014-09-30 |
| 8519402 | Structure, structure and method of latch-up immunity for high and low voltage integrated circuits | — | 2013-08-27 |
| 8487379 | Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications | Max G. Levy | 2013-07-16 |
| 8423936 | Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors | — | 2013-04-16 |
| 8420518 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2013-04-16 |
| 8410534 | Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact | — | 2013-04-02 |
| 8390074 | Structure and method for latchup improvement using through wafer via latchup guard ring | — | 2013-03-05 |
| 8362564 | Isolated epitaxial modulation device | Yu Li | 2013-01-29 |
| 8301288 | Optimized scheduling based on sensitivity data | Brian T. Denton, Cuc K. Huynh, Shreesh S. Tandel | 2012-10-30 |
| 8232625 | ESD network circuit with a through wafer via structure and a method of manufacture | — | 2012-07-31 |
| 8227318 | Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation | Max G. Levy, Natalie B. Feilchenfeld, Richard A. Phelps, BethAnn Rainey, James A. Slinkman +7 more | 2012-07-24 |