Issued Patents All Time
Showing 26–50 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8193563 | High power device isolation and integration | Jeffrey P. Gambino, Michael J. Zierak | 2012-06-05 |
| 8188570 | Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications | Max G. Levy | 2012-05-29 |
| 8178925 | Semiconductor diode structure operation method | — | 2012-05-15 |
| 8171435 | Integrated circuit structure incorporating an inductor, an associated design method and an associated design system | Zhong-Xiang He, Robert M. Rassel | 2012-05-01 |
| 8143671 | Lateral trench FETs (field effect transistors) | — | 2012-03-27 |
| 8138579 | Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology | Xuefeng Liu, Robert M. Rassel | 2012-03-20 |
| 8129772 | Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact | — | 2012-03-06 |
| 8114750 | Lateral diffusion field effect transistor with drain region self-aligned to gate electrode | Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Michael J. Zierak | 2012-02-14 |
| 8110875 | Structure for charge dissipation during fabrication of integrated circuits and isolation thereof | John J. Ellis-Monaghan, Jeffrey P. Gambino, Timothy D. Sullivan | 2012-02-07 |
| 8110853 | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication | — | 2012-02-07 |
| 8108822 | Methodology for placement based on circuit function and latchup sensitivity | — | 2012-01-31 |
| 8105924 | Deep trench based far subcollector reachthrough | Bradley A. Orner, Robert M. Rassel, David C. Sheridan | 2012-01-31 |
| 8108817 | Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors | — | 2012-01-31 |
| 8088656 | Fabricating ESD devices using MOSFET and LDMOS | — | 2012-01-03 |
| 8054597 | Electrostatic discharge structures and methods of manufacture | Ephrem G. Gebreselasie | 2011-11-08 |
| 8044510 | Product and method for integration of deep trench mesh and structures under a bond pad | Ephrem G. Gebreselasie, William T. Motsiff, Wolfgang Sauter | 2011-10-25 |
| 8035190 | Semiconductor devices | Xuefeng Liu, Robert M. Rassel | 2011-10-11 |
| 8017995 | Deep trench semiconductor structure and method | Jeffrey P. Gambino, Benjamin T. Voegeli, Michael J. Zierak | 2011-09-13 |
| 8017471 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry | Phillip F. Chapman, David S. Collins | 2011-09-13 |
| 8015538 | Design structure with a deep sub-collector, a reach-through structure and trench isolation | Douglas D. Coolbaugh, Xuefeng Liu, Robert M. Rassel, David C. Sheridan | 2011-09-06 |
| 8015518 | Structures for electrostatic discharge protection for bipolar semiconductor circuitry | — | 2011-09-06 |
| 7989306 | Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate | Xuefeng Liu, Robert M. Rassel | 2011-08-02 |
| 7989282 | Structure and method for latchup improvement using through wafer via latchup guard ring | — | 2011-08-02 |
| 7977714 | Wrapped gate junction field effect transistor | John J. Ellis-Monaghan, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak | 2011-07-12 |
| 7956412 | Lateral diffusion field effect transistor with a trench field plate | Natalie B. Feilchenfeld, Jeffrey P. Gambino, Louis D. Lanzerotti, Benjamin T. Voegeli, Michael J. Zierak | 2011-06-07 |