Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10348183 | Semiconductor device and actuator system | — | 2019-07-09 |
| 10224969 | Transmitter circuit, semiconductor apparatus and data transmission method | Koichi Takeda, Hirokazu Nagase | 2019-03-05 |
| 10115684 | Semiconductor device | Shinichi Uchida, Tadashi Maeda, Kazuo Henmi | 2018-10-30 |
| 9813084 | Transmitter circuit, semiconductor apparatus and data transmission method | Koichi Takeda, Hirokazu Nagase | 2017-11-07 |
| 9589887 | Semiconductor device | Shinichi Uchida, Tadashi Maeda, Kazuo Henmi | 2017-03-07 |
| 9466591 | Semiconductor device | Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka | 2016-10-11 |
| 9252200 | Semiconductor device | Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka | 2016-02-02 |
| 8010557 | Retrieving method for fixed length data | — | 2011-08-30 |
| 7565343 | Search apparatus and search management method for fixed-length data | — | 2009-07-21 |
| 7541765 | Motor controlling circuit and method | — | 2009-06-02 |
| 7469243 | Method and device for searching fixed length data | Masaya Mori, Yoshihisa Takatsu, Toshio Sunaga | 2008-12-23 |
| 7460538 | Communication control apparatus and method for searching an internet protocol address | Yoshihisa Takatsu, Masaya Mori, Toshio Sunaga | 2008-12-02 |
| 7124278 | Information processing device and method, program, data structure, and computer-readable recording medium | Masaya Mori, Yoshihisa Takatsu, Toshio Sunaga | 2006-10-17 |
| 7093067 | DRAM architecture enabling refresh and access operations in the same bank | Toshio Sunaga | 2006-08-15 |
| 7061818 | Memory and refresh method for memory | Toshio Sunaga | 2006-06-13 |
| 6977857 | DRAM and refresh method thereof | Masaya Mori, Toshio Sunaga | 2005-12-20 |
| 6961802 | Data input/output device, memory system, data input/output circuit, and data input/output method | Masaya Mori | 2005-11-01 |
| 6925028 | DRAM with multiple virtual bank architecture for random row access | Kohji Hosokawa, Toshio Sunaga | 2005-08-02 |
| 6898661 | Search memory, memory search controller, and memory search method | Masaya Mori, Toshio Sunaga | 2005-05-24 |
| 6865136 | Timing circuit and method of changing clock period | Toshio Sunaga, Masaya Mori | 2005-03-08 |
| 6650573 | Data input/output method | Toshio Sunaga | 2003-11-18 |
| 6545932 | SDRAM and method for data accesses of SDRAM | Toshio Sunaga | 2003-04-08 |
| 6252794 | DRAM and data access method for DRAM | Toshio Sunaga | 2001-06-26 |
| 6085300 | DRAM system with simultaneous burst read and write | Toshio Sunaga | 2000-07-04 |
| 5553252 | Device for controlling data transfer between chips via a bus | Kazunori Takayanagi | 1996-09-03 |