Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and structures for improving substrate loss and linearity in SOI substrates

Method and structures for improving substrate loss and linearity in SOI substrates

US Patent 8089126 · Granted Jan 3, 2012

Estimated economic value: $8,800,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integration of compound-semiconductor-based devices and silicon-based devices2025
Switches in bulk substrate2025
Field effect transistor with shallow trench isolation features within source/dra2025
Heterojunction bipolar transistor with buried trap rich isolation region2025
High electron mobility transistors having barrier liners and integration schemes2025
Bipolar transistor with stepped emitter2025
Contact-over-active-gate transistor structures with contacts landed on enlarged 2025
Heterojunction bipolar transistor with buried trap rich isolation region2024
Field effect transistor2024
Semiconductor structure with semiconductor-on-insulator region and method2024
IC structure including porous semiconductor layer in bulk substrate adjacent tre2024
Integrated circuit structure with through-metal through-substrate interconnect a2024