Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8594826 | Method and system for evaluating a machine tool operating characteristics | Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin J. Mackey +6 more | 2013-11-26 |
| 8285414 | Method and system for evaluating a machine tool operating characteristics | Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin J. Mackey +6 more | 2012-10-09 |
| 8212332 | Bias-controlled deep trench substrate noise isolation integrated circuit device structures | Phillip F. Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman +1 more | 2012-07-03 |
| 8021941 | Bias-controlled deep trench substrate noise isolation integrated circuit device structures | Phillip F. Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman +1 more | 2011-09-20 |
| 7309898 | Method and apparatus for providing noise suppression in an integrated circuit | Steven H. Voldman | 2007-12-18 |
| 7246055 | Open system for simulation engines to communicate across multiple sites using a portal methodology | — | 2007-07-17 |
| 7139990 | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction | Yue Tan, Jean-Oliver Plouchart, Lawrence F. Wagner, Jr., Mohamed Talbi, John M. Safran +1 more | 2006-11-21 |
| 7089512 | Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits | Joseph A. Iadanza | 2006-08-08 |
| 7020857 | Method and apparatus for providing noise suppression in a integrated circuit | Steven H. Voldman | 2006-03-28 |
| 7000214 | Method for designing an integrated circuit having multiple voltage domains | Joseph A. Iadanza, Sebastian T. Ventrone, Ivan L. Wemple | 2006-02-14 |
| 6954920 | Method, program product, and design tool for automatic transmission line selection in application specific integrated circuits | Peter Joel Jenkins, Sebastian T. Ventrone | 2005-10-11 |
| 6950997 | Method and system for low noise integrated circuit design | Carl Dickey, Scott Parker | 2005-09-27 |
| 6865725 | Method and system for integrated circuit design | Carl Dickey, Donald L. Jordan, Sue Ellen Strang | 2005-03-08 |
| 6825490 | On chip resistor calibration structure and method | Terence B. Hook, Stephen D. Wyatt | 2004-11-30 |
| 6826025 | Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit | Steven H. Voldman | 2004-11-30 |
| 6744112 | Multiple chip guard rings for integrated circuit and chip guard ring interconnect | Jeffrey B. Johnson, Alvin J. Joseph, Parker A. Robinson, Dennis Whittaker | 2004-06-01 |