Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7863691 | Merged field effect transistor cells for switching | Randy L. Wolf | 2011-01-04 |
| 7139990 | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction | Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Mohamed Talbi, John M. Safran +1 more | 2006-11-21 |
| 6562666 | Integrated circuits with reduced substrate capacitance | Heemyong Park, Fariborz Assaderaghi, Jack A. Mandelman, Ghavam G. Shahidi | 2003-05-13 |
| 6490546 | Method for obtaining DC convergence for SOI FET models in a circuit simulation program | Richard Daniel Kimmel | 2002-12-03 |
| 6141632 | Method for use in simulation of an SOI device | George E. Smith, III, Fariborz Assaderaghi, Paul D. Muench, Timothy Walters | 2000-10-31 |
| 6023577 | Method for use in simulation of an SOI device | George E. Smith, III, Timothy Walters, Fariborz Assaderaghi | 2000-02-08 |
| 5770881 | SOI FET design to reduce transient bipolar current | Mario M. Pelella, Fariborz Assaderaghi | 1998-06-23 |
| 5446312 | Vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper | 1995-08-29 |
| 5371022 | Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper | 1994-12-06 |
| 5341023 | Novel vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper | 1994-08-23 |
| 5258640 | Gate controlled Schottky barrier diode | Chang-Ming Hsieh, Louis L. Hsu, Phung T. Nguyen | 1993-11-02 |
| 5109524 | Digital processor with a four part data register for storing data before and after data conversion and data calculations | Korbin S. Van Dyke, Wayne Burleson, Robert D. Hemming, John P. Guadagna | 1992-04-28 |
| 4862346 | Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses | Korbin S. Van Dyke, Wayne Burleson, Robert D. Hemming, John P. Guadagna | 1989-08-29 |
| 4857882 | Comparator array logic | Wayne Burleson, John P. Guadagna | 1989-08-15 |
| 4852038 | Logarithmic calculating apparatus | Wayne Burleson, Korbin S. Van Dyke | 1989-07-25 |
| 4626825 | Logarithmic conversion apparatus | Wayne Burleson, Korbin S. Van Dyke | 1986-12-02 |
| 4415767 | Method and apparatus for speech recognition and reproduction | Stephen P. Gill, Gregory Frye, Klaus-Peter A. Bantowsky | 1983-11-15 |