Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6144081 | Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures | Louis L. Hsu, Lyndon R. Logan, Jack A. Mandelman, Seiki Ogura | 2000-11-07 |
| 6107141 | Flash EEPROM | Louis L. Hsu, Seiki Ogura | 2000-08-22 |
| 5962895 | SOI transistor having a self-aligned body contact | Klaus D. Beyer, Taqi Nasser Buti, Louis L. Hsu | 1999-10-05 |
| 5910912 | Flash EEPROM with dual-sidewall gate | Louis L. Hsu, Seiki Ogura | 1999-06-08 |
| 5874764 | Modular MOSFETS for high aspect ratio applications | Somnuk Ratanaphanyarat, Shao-fu Sanford Chu, Louis L. Hsu | 1999-02-23 |
| 5774411 | Methods to enhance SOI SRAM cell stability | Louis L. Hsu, Jack A. Mandelman, Mario M. Pelella | 1998-06-30 |
| 5729039 | SOI transistor having a self-aligned body contact | Klaus D. Beyer, Taqi Nasser Buti, Louis L. Hsu | 1998-03-17 |
| 5721144 | Method of making trimmable modular MOSFETs for high aspect ratio applications | Somnuk Ratanaphanyarat, Shao-fu Sanford Chu, Louis L. Hsu | 1998-02-24 |
| 5567553 | Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures | Louis L. Hsu, Lyndon R. Logan | 1996-10-22 |
| 5528062 | High-density DRAM structure on soi | Louis L. Hsu, Seiki Ogura | 1996-06-18 |
| 5521399 | Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit | Shao-fu Sanford Chu, Louis L. Hsu, Kyong-Min Kim, Shaw-Ning Mei | 1996-05-28 |
| 5484738 | Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits | Shao-fu Sanford Chu, Louis L. Hsu, Kyong-Min Kim, Shaw-Ning Mei | 1996-01-16 |
| 5466625 | Method of making a high-density DRAM structure on SOI | Louis L. Hsu, Seiki Ogura | 1995-11-14 |
| 5446312 | Vertical-gate CMOS compatible lateral bipolar transistor | Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1995-08-29 |
| 5405795 | Method of forming a SOI transistor having a self-aligned body contact | Klaus D. Beyer, Taqi Nasser Buti, Louis L. Hsu | 1995-04-11 |
| 5389559 | Method of forming integrated interconnect for very high density DRAMs | Louis L. Hsu, Toshio Mii, Seiki Ogura, Joseph F. Shepard, Jr. | 1995-02-14 |
| 5385850 | Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer | Jack O. Chu, Victor R. Nastasi, Martin Revitz, Paul A. Ronsheim | 1995-01-31 |
| 5371022 | Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor | Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1994-12-06 |
| 5366923 | Bonded wafer structure having a buried insulation layer | Klaus D. Beyer, Louis L. Hsu, Tsorng-Dih Yuan | 1994-11-22 |
| 5340759 | Method of making a vertical gate transistor with low temperature epitaxial channel | Louis L. Hsu, Seiki Ogura | 1994-08-23 |
| 5341023 | Novel vertical-gate CMOS compatible lateral bipolar transistor | Louis L. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1994-08-23 |
| 5315151 | Transistor structure utilizing a deposited epitaxial base region | Louis L. Hsu, Victor J. Silvestri | 1994-05-24 |
| 5313094 | Thermal dissipation of integrated circuits using diamond paths | Klaus D. Beyer, Louis L. Hsu, David E. Kotecki, Tsoring-Dih Yuan | 1994-05-17 |
| 5283456 | Vertical gate transistor with low temperature epitaxial channel | Louis L. Hsu, Seiki Ogura | 1994-02-01 |
| 5276338 | Bonded wafer structure having a buried insulation layer | Klaus D. Beyer, Louis L. Hsu, Tsorng-Dih Yuan | 1994-01-04 |