Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9099461 | Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure | Michael P. Chudzik, Min Dai, Jinping Liu, Joseph F. Shepard, Jr., Shahab Siddiqui | 2015-08-04 |
| 8900973 | Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion | Nathaniel Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta +2 more | 2014-12-02 |
| 8347741 | Specimen handling apparatus | Michael Hatzistergos, Jonathan Levy, Christopher M. Molella, Dmitriy Shneyder, Vincent Vazquez | 2013-01-08 |
| 8158449 | Particle emission analysis for semiconductor fabrication steps | Cyril Cabral, Jr., Michael S. Gordon, Jeff McMurray, Cristina Plettner | 2012-04-17 |
| 8114748 | Shallow extension regions having abrupt extension junctions | Kam-Leung Lee | 2012-02-14 |
| 7071103 | Chemical treatment to retard diffusion in a semiconductor overlayer | Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee +5 more | 2006-07-04 |
| 6749684 | Method for improving CVD film quality utilizing polysilicon getterer | Huajie Chen, Dan M. Mocuta, Richard J. Murphy, David M. Rockwell | 2004-06-15 |
| 6635517 | Use of disposable spacer to introduce gettering in SOI layer | Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta +1 more | 2003-10-21 |
| 6509241 | Process for fabricating an MOS device having highly-localized halo regions | Heemyong Park, Anda C. Mocuta | 2003-01-21 |
| 6399434 | Doped structures containing diffusion barriers | Susan E. Chaloux, Johnathan E. Faltermeier, Ulrike Gruening, Rajarao Jammy, Christopher C. Parks +2 more | 2002-06-04 |
| 6387782 | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan | 2002-05-14 |
| 6335262 | Method for fabricating different gate oxide thicknesses within the same chip | Scott W. Crowder, Anthony G. Domenicucci, Liang Han, Michael Hargrove | 2002-01-01 |
| 6329704 | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan | 2001-12-11 |
| 6194736 | Quantum conductive recrystallization barrier layers | Susan E. Chaloux, Tze-Chiang Chen, Johnathan E. Faltermeier, Ulrike Gruening, Rajarao Jammy +4 more | 2001-02-27 |
| 6114257 | Process for modified oxidation of a semiconductor substrate using chlorine plasma | — | 2000-09-05 |
| 5656514 | Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile | David C. Ahlgren, Jack O. Chu, Martin Revitz, Mary J. Saccamango, David Sunderland | 1997-08-12 |
| 5385850 | Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer | Jack O. Chu, Chang-Ming Hsieh, Victor R. Nastasi, Martin Revitz | 1995-01-31 |
| 5194397 | Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface | Robert K. Cook, Ronald W. Knepper, Subodh K. Kulkarni, Russell C. Lange, Seshadri Subbanna +2 more | 1993-03-16 |