Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11991877 | DRAM circuitry and method of forming DRAM circuitry | Toshihiko Miyashita | 2024-05-21 |
| 10720363 | Method of forming vertical transistor device | Julien Ryckaert, Naoto Horiguchi, Trong Huynh Bao | 2020-07-21 |
| 10522552 | Method of fabricating vertical transistor device | Julien Ryckaert, Naoto Horiguchi, Trong Huynh Bao | 2019-12-31 |
| 9673197 | FinFET with constrained source-drain epitaxial region | Brian J. Greene, Arvind Kumar | 2017-06-06 |
| 9536879 | FinFET with constrained source-drain epitaxial region | Brian J. Greene, Arvind Kumar | 2017-01-03 |
| 9461050 | Self-aligned laterally extended strap for a dynamic random access memory cell | Byeong Y. Kim | 2016-10-04 |
| 9443854 | FinFET with constrained source-drain epitaxial region | Brian J. Greene, Arvind Kumar | 2016-09-13 |
| 9299780 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Brian J. Greene, Arvind Kumar | 2016-03-29 |
| 9252215 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Brian J. Greene, Arvind Kumar | 2016-02-02 |
| 9093275 | Multi-height multi-composition semiconductor fins | Brian J. Greene, Augustin J. Hong, Byeong Y. Kim | 2015-07-28 |
| 9059194 | High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control | Colin J. Brodsky, Anne C. Friedman, Herbert L. Ho, Byeong Y. Kim, Garrett W. Oakley +1 more | 2015-06-16 |
| 8168971 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain | Dureseti Chidambarrao, Anda C. Mocuta, Carl Radens | 2012-05-01 |
| 7723750 | MOSFET with super-steep retrograded island | Huilong Zhu, Effendi Leobandung, Anda C. Mocuta | 2010-05-25 |
| 7691698 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain | Dureseti Chidambarrao, Anda C. Mocuta, Carl Radens | 2010-04-06 |
| 7550370 | Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density | Huajie Chen, Stephen W. Bedell, Devendra K. Sadana | 2009-06-23 |
| 7528027 | Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel | Huilong Zhu, Mahender Kumar, Ravikumar Ramachandran, Wenjuan Zhu | 2009-05-05 |
| 7498602 | Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets | Huilong Zhu, Bruce B. Doris | 2009-03-03 |
| 7268049 | Structure and method for manufacturing MOSFET with super-steep retrograded island | Huilong Zhu, Effendi Leobandung, Anda C. Mocuta | 2007-09-11 |
| 7202132 | Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs | Huilong Zhu, Bruce B. Doris | 2007-04-10 |
| 7071103 | Chemical treatment to retard diffusion in a semiconductor overlayer | Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee +5 more | 2006-07-04 |
| 6958286 | Method of preventing surface roughening during hydrogen prebake of SiGe substrates | Huajie Chen, Richard J. Murphy, Stephan W. Bedell, Devendra K. Sadana | 2005-10-25 |
| 6916698 | High performance CMOS device structure with mid-gap metal gate | Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Huajie Chen | 2005-07-12 |
| 6762469 | High performance CMOS device structure with mid-gap metal gate | Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Huajie Chen | 2004-07-13 |
| 6749684 | Method for improving CVD film quality utilizing polysilicon getterer | Huajie Chen, Richard J. Murphy, Paul A. Ronsheim, David M. Rockwell | 2004-06-15 |